本篇論文提出一顆具有特殊指令集的數位信號處理器晶片，專門應用於語音信號辨識之使用。利用數位信號處理器的指令集，將語音信號線性預測編碼(Linear Predictive Coding)演算法以及動態時間校準(Dynamic Timing Warping)辨識演算法實現於數位信號處理器。運用硬體電路搭配軟體演算法整合設計的方式，設計出最佳的電路架構以及專屬的特殊指令集。在電路架構設計，處理器具有雙算數邏輯運算單元(ALU)，雙算數邏輯運算單元之設計使得處理器具有平行運算之能力。應用UMC 0.18um 標準單元(standard cell)合成出處理器電路，晶片面積約為4.29 ，工作頻率為100MHz。

This thesis proposes a new application specific instruction set processor for speech recognition. The processor is designed to process linear predictive coding and dynamic timing warping speech recognition. We use hardware-software codesign methodology to optimize the processor architecture and instruction set. We design dual-ALU architecture in the DSP. The dual-ALU architecture provides parallel calculation capability. The processor is synthesized by UMC 0.18um cell library. The die size of the processor is approximately 4.29 . The processor can work at 100MHz.

Abstract in Chinese i
Abstract in English ii
Contents iii
List of tables v
List of figures vi
1. Introduction 1
1.1 Introduction of speech recognition 1
1.2 Introduction of DSP processor 3
1.3 Motivation 7
1.4 Thesis organization 7
2. DTW Speech Recognition 8
2.1 Linear predictive model and analysis 8
2.1.1 LPC model 8
2.1.2 LPC analysis 9
2.2 Cepstral analysis 11
2.3 Dynamic time warping speech recognition 12
3. DSP Architecture Design 15
3.1 Processor architecture overview 15
3.2 Pipeline operations 22
3.3 Address modes and instruction set 26
3.3.1 Address modes 26
3.3.2 Instruction set 27
3.4 Data format and division algorithm 32
3.4.1 Data format 32
3.4.2 Division algorithm 33
4. Implementation and Simulation Results 34
4.1 System specification 34
4.2 Design flow 35
4.3 Test consideration 37
4.4 Implementation result and experiment results 38
5. Conclusions 43
Bibliography 44

[1] John R. Deller, Jr., John G. Proakis, John H. L. Hansen, Discrete-time processing of speech signals, IEEE press, 2000.
[2] Douglas O’shaughnessy, Speech communications: human and machine, 2nd Edition, IEEE press, 2000.
[3] Lawrence Rabiner, Biing-Hwang Juang, Fundamentals of speech recognition, Prentice Hall inc., New Jersey, 1993.
[4] Margarida F. Jacome, Gustavo de Veciana, “Design challenges for new application specific processors,” IEEE Design & Test of Computer Magazine, vol. 17, pp. 40-50, June 2000.
[5] Asawaree Kalavade, Edward A. Lee, “A hardware-software codesign methodology for DSP applications,” IEEE Design & Test of Computer Magazine, vol. 10, pp. 16-28, Sept. 1993.
[6] Carolyn Kuttner, “Hardware-software codesign using processor synthesis,” IEEE Design & Test of Computer Magazine, vol. 13, pp. 43-53, Full 1996.
[7] Douglas O’Shaughnessy, “Linear predictive coding,” IEEE Potentials, vol. 7, pp.29-32, Feb 1988.
[8] H. Sakoe, S. Chiba, “Dynamic programming algorithm optimization for spoken word recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26. pp. 43-49, Feb 1978.
[9] Harvey F. Silverman, David P. Morgan, “The application of dynamic programming to connected speech recognition,” IEEE ASSP Magazine, vol. 7, pp. 6-25, July 1990.
[10] L. Rabiner, A. Rosenberg, S. Levinson, “Conderations in dynamic time warping algorithms for discrete word recognition” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26. pp. 575-582, Dec 1978.
[11] UMC 0.18 um Process High-speed Single-Port SRAM (HS-SRAM-SP) Generator Manual, Artisan Components, Inc. August 2000.
[12] David R. Smith, Paul D. Franzon, Verilog Styles for synthesis of digital systems, Prentice Hall inc., New Jersey, 2000.
[13] Donald E. Thomas and Philip Moorby, The Verilog Hardware Description Language, Kluwer Acadmic Publishers, 1998.
[14] Design Compiler User Guide, Synopsys, Inc. Dec 2003.
[15] Using Tcl with Synopsys tools, Synopsys, Inc. March 2003.
[16] Astro User Guide, Synopsys, Inc. Sep 2003.
[17] TurboBIST-Memory SRAM Built-In-Self-Test Generator Reference Manual, SynTest Technologies, Inc. version 1.4, Jan 2004.
[18] DFT Compiler Scan Synthesis User Guide, Synopsys, Inc. June 2003.