臺灣博碩士論文加值系統

當積體電路製程推進到奈米(sub-100nm)元件世代，絕緣層上覆矽技術的使用將是可行性的替代方案之一。當元件尺寸縮小到100奈米時，閘極介電層的等效氧化層厚度必須薄於20埃以下。然而，在如此薄氧化層的絕緣層上覆矽元件中，軟式崩潰所引發之可靠性問題將是異常重要。

本篇論文將針對超薄氧化層絕緣層上覆矽金氧半場效電晶體中軟式崩潰所引發之可靠性議題作一系列的探討。首先，吾人探討超薄閘極氧化層中直接穿隧區域的電荷傳輸機制。主要的閘極穿隧漏電流可以分成源/汲極穿隧電流和基底極穿隧電流。在此吾人利用一套量子化電荷傳輸機制來解釋源/汲極電流和用古典的電荷傳輸機制來解釋基底極電流。為了精準的模擬穿隧電流，吾人藉由解波松和薛丁格聯立方程式來計算氧化層電場。在超薄氧化層絕緣層上覆矽金氧半場效電晶體中，由於浮動基底極的原因，這些穿隧漏電流將對可靠性造成一些新奇的影響。

接下來，在浮動基底極絕緣層上覆矽元件中，吾人知道大量的基底漏電流所造成的基底電位的調變和所導致不可避免的磁滯效應已被廣泛的討論。由於氧化層崩潰將增加基底極的穿隧漏電流，所以在浮動基底極的超薄閘極氧化層絕緣層上覆矽元件中，崩潰位置對臨界電壓磁滯現象的影響將在這部分探討。吾人將發表兩種在關閉狀態的金氧半電晶體中氧化層崩潰增強磁滯現象的模型。吾人所提供的基底充電機制和實驗結果相符。在浮動基底結構下的超薄閘極氧化層部份空乏絕緣層上覆矽金氧半場效電晶體中，軟式崩潰增強的磁滯現象將成為一種嚴重的可靠性議題。

再者，吾人發現在浮動基底絕緣層上覆矽金氧半場效電晶體中通道軟式崩潰導致一種新的低頻汲極電流雜訊退化現象。這種額外的雜訊來源來自於通道軟式崩潰導致大量基底極的價帶電子穿隧電流產生微量的白雜訊放大所致。在超薄閘極氧化層類比絕緣層上覆矽元件中，即使在操作電壓小於一伏特，通道軟式崩潰增加額外的雜訊仍會發生並將成為一個重要的可靠性問題。

最後，直接穿隧效應也會對超薄氧化層的崩潰及元件之毀壞產生影響。一般來說，元件的毀壞與否是由氧化層崩潰所造成破壞程度所決定，代表破壞程度較低的氧化層漏電流對實際電路應用而言，並不會造成任何操作上的影響。吾人在p型超薄氧化層絕緣層上覆矽電晶體中，針對浮動基底極對氧化層崩潰的破壞程度作完整之研究。在p型超薄氧化層元件中，吾人發現了正偏壓基底極操作模式下所產生的加速崩潰破壞。當氧化層初崩潰時，高能量的通道電洞在正偏基底極時產生較大的電動加壓電流，進而使得氧化層產生更大的破壞。藉由熱載子光激發實驗及熱電洞在通道能階上的分佈分析，吾人成功地解釋出此基底極偏壓相依性。吾人並預測此種崩潰破壞將對浮動基底超薄閘極氧化層絕緣層上覆矽p型金氧半場效電晶體產生新的可靠性議題。

The silicon-on-insulator (SOI) technology is a promising candidate of IC manufacture required for sub-100nm CMOS devices. As device size shrinks below 100nm, the effective oxide thickness of gate dielectric must scale below 20Å. While, a great reliability concern induced by soft breakdown (SBD) in such thin oxides SOI devices is being aroused.
The objective of this dissertation is to investigate soft breakdown induced reliability issues in such ultra-thin oxide SOI MOSFETs. First of all, the charge transport mechanisms of oxide in direct tunneling regime is investigated. The gate tunneling leakage current can be separated by source/drain tunneling current and substrate tunneling current. In this work, a quantum charge transport mechanism is proposed to explain the source/drain current. And, a classical charge transport mechanism is proposed to explain the substrate current. To calculate the tunneling current accurately, the oxide electric field is simulated by means of solving the combined Poisson and Schrodinger equations. These tunneling leakage currents may bring about some reliability concerns in floating body ultra-thin oxide SOI MOSFETS.
Further, substrate leakage current has been known to cause substrate bias variation and induce unavoidable hysteresis effects in floating body SOI devices. Since oxide breakdown can enhance substrate tunneling leakage current, the impact of breakdown location on threshold voltage hysteresis in ultra-thin oxide SOI devices is investigated in this part. Two breakdown enhanced hysteresis modes in off-state CMOS are identified. The proposed body charging mechanisms are verified by our measurement results. The SBD enhanced hysteresis effect would be a serious reliability subject in ultra-thin oxide MOSFETs with floating body configuration.
Moreover, a new low frequency drain current noise source in floating body SOI nMOSFETs caused by channel soft breakdown is studied. The excess noise originates from channel soft breakdown enhanced valence band electron tunneling and the amplification by the small white noise of the substrate current. The c-SBD enhanced excess noise may occur even with supply voltage less than 1.0V and would be an important reliability problem in analog applications.
Finally, a large direct tunneling current can decrease oxide time-to-breakdown and limit oxide further scaling. Actually in most circuits, the failure criterion is determined by the hardness of oxide breakdown. In this part, floating body enhanced breakdown progression in ultra-thin oxide SOI pMOS is proposed. The enhanced progression is attributed to the increase of hole tunneling current resulting from breakdown induced channel carrier heating. The substrate bias dependence of post-breakdown hole tunneling current is confirmed through the calculation of channel hole distribution in sub-bands. This observed phenomenon is significant to ultra-thin gate oxide reliability in floating body SOI pMOSFETs.

Chinese Abstract i
English Abstract iii
Acknowledgements v
Contents vi
Figure Captions ix
Table Captions xiv

Chapter 1 Introduction 1

Chapter 2 Simulation of Charge Transport in Ultra-Thin Oxide MOSFETs 5
2.1 Introduction 5
2.2 Surface Quantization and Gate Capacitance Modeling 6
2.3.1 Simulation Model for Potential Distribution 6
2.3.2 Self Consistent Solution of Schrodinger's and Poisson's Equations 8
2.3.3 Gate Capacitance Modeling 8
2.3 Source/Drain Tunneling Current Modeling 17
2.3.1 Transport of Conduction Band Electrons 17
2.3.2 Simulated and measured results 20
2.4 Substrate Tunneling Current Modeling 25
2.4.1 Transport of Valence Band Electrons 25
2.4.2 Simulated and Measured Result 26
2.5 Summary 27


Chapter 3 Soft Breakdown Enhanced Hysteresis Effects in Ultra-Thin Oxide SOI MOSFETs 31
3.1 Introduction 31
3.2 Device Structure and Characterization 32
3.3 Modes of SBD Enhanced Hysteresis 38
3.4 Results and Discussion 41
3.5 Summary 42

Chapter 4 Soft Breakdown Enhanced Excess Low- Frequency Noise in Ultra-Thin Oxide SOI n-MOSFETs 50
4.1 Introduction 50
4.2 Excess Low-Frequency Noise Model in SOI MOSFETs 51
4.3 Kink Effect Induced Excess Low-Frequency Noise 60
4.4 Channel Soft Breakdown Enhanced Excess Low- Frequency Noise 66
4.5 Summary 68

Chapter 5 Floating Body Accelerated Oxide Breakdown Progression in Ultra-Thin Oxide SOI p-MOSFETs 73
5.1 Introduction 73
5.2 Devices and Experiment 74
5.3 Result and Discussion 76
5.3.1 A Shorter tfail in SOI pMOSFETs 76
5.3.2 Mechanism of Enhanced BD Progression in SOI 76
5.3.3 BD Caused Carrier Heating 77

5.4 The Impact of Gate Stress Bias 88
5.4 Summary 88

Chapter 6 Conclusions 93
References 95
Vita 108
Publication Lists 109

Chapter 1
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[1.9] Tahui Wang, C.W. Tsai, M.C. Chen, C.T. Chan, H.K. Chiang, S. Huang Lu, H.C. Hu, T.F. Chen, C.K. Yang, M.T. Lee, D.Y. Wu, J.K. Chen, S.C. Chien and S.W. Sun, “Negative Substrate Bias Enhanced Breakdown Hardness in Ultra-Thin Oxide pMOSFETs “ in 2003 IRPS Proc., p.437, 2003.
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Chapter 2
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Chapter 3
[3.1] T. Ouisse, G. Ghibaudo, J. Brini, S. Cristoloveanu and G. Borel, “Investigation of floating body effects in silicon-on-insulator metal-oxide-semiconductor field-effect transistors”, in Journal of Applied Physics, vol. 70, no.7, p. 3912 1991.
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Chapter 4
[4.1] T. Ouisse, G. Ghibaudo, J. Brini, S. Cristoloveanu and G. Borel, “Investigation of floating body effects in silicon-on-insulator metal-oxide-semiconductor field-effect transistors”, in Journal of Applied Physics, vol. 70, no.7, p. 3912 1991.
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Chapter 5
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