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研究生:左仲先
研究生(外文):Chung-Hsien Tso
論文名稱:應用於切換式直流至直流轉換器之高性能互補金氧半控制器
論文名稱(外文):HIGH PERFORMANCE CMOS CONTROLLERS FOR SWITCHING-MODE DC-DC CONVERTERS
指導教授:吳錦川
指導教授(外文):Jiin-Chuan Wu
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:93
語文別:英文
論文頁數:163
中文關鍵詞:切換式轉換器直流至直流轉換器自由運行控制相鎖迴路漣漪控制固定開啟時間控制比例式電流回授數位控制類比數位轉換器
外文關鍵詞:switching-mode converterDC-DC converterfree-running controlphase-locked loopPLLripple controlconstant on-time controlproportional current feedbackVRMdigital controlA/D converter
相關次數:
  • 被引用被引用:8
  • 點閱點閱:682
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  • 下載下載:1
  • 收藏至我的研究室書目清單書目收藏:0
本論文針對切換式直流至直流轉換器提出數種創新之高性能控制器。為了要達到快速暫態反應、高效率、穩定運作以及固定的切換頻率等需求,新型控制器的分析與設計在本論文裡有完整的探討,並利用CMOS類比及數位混合式積體電路技術實現控制電路。

現存之自由運行控制電路具有架構簡單和反應極為快速之優點,然而切換頻率不固定,因此無法運用在對電磁干擾敏感的裝置中,同時相關的論文質與量皆相當缺乏,在理論分析方面仍有進一步探討的空間。在本論文中對於常見的兩種自由運行控制型式--漣漪控制和固定開啟時間控制進行理論研究,並針對缺點提出改進的電路架構。
在固定開啟時間控制方面,設計可依據輸入輸出電壓調整開啟時間的電路,因此切換頻率幾乎不隨輸入輸出電壓以及負載電流變動。在論文中探討自由運行控制的不穩定現象,容易被回授信號上的雜訊干擾,因此提出創新的補償電路,可改善頻率響應以及雜訊免疫能力,利用內建積分器產生的斜坡信號用來觸發比較器,具有良好的雜訊免疫能力,可以達到穩定且快速的動作。控制電路利用1微米的互補式金氧半導體積體電路技術來實現,包含輸入輸出接腳的面積為5.2毫米平方,實驗結果顯示暫態反應十分快速,在輸入電壓5伏特,輸出電壓2.476伏特,負載電流10毫安培至3安培的情況下,效率可達86 %至93 %,負載穩壓度和線穩壓度分別為0.032 %/A和0.034 %/V,均優於傳統電壓模式和電流模式的脈寬調變控制方式。

在漣漪控制方面,提出了嶄新的方法,利用相鎖迴路調整延遲,用以鎖定切換頻率,並針對buck和boost兩種功率級分別提出電壓模式與電流模式之漣漪控制器。穩態反應分析、輸出電壓電流轉換函數、切換頻率函數以及頻率響應函數在論文中有推導及分析,根據頻率響應設計出補償網路,分析漣漪控制之各種特性。同時,將切換頻率與延遲的關係線性化之後,可得到一個線性模型,根據此模型,我們可以設計迴路參數和分析相鎖迴路的穩定度。穩壓器電路經由SPICE模擬,buck穩壓器在輸入20伏特輸出1.5伏特的情況下,穩態切換頻率鎖定300 kHz,負載穩壓度和線穩壓度分別為0.0046 %/A和0.028 %/V;boost穩壓器在輸入2.4伏特輸出3.3伏特的情況下,穩態切換頻率鎖定300 kHz,負載穩壓度和線穩壓度分別為0.96 %/A和0.75 %/V,其他模擬結果也包含在本論文內。

傳統之類比式控制器存在調整困難,容易隨製程參數與外在環境漂移之缺點,數位式控制器則受限於電路數量較多與成本較高,針對此一問題,提出一種混合式控制電路,利用比例式電流回授技術加速電源穩壓器之暫態反應,配合特別電路設計,簡化類比數位轉換與數位運算電路,具有架構簡單與高性能之優點,且容易調整控制參數。一般數位類比混合電路多利用電晶體等級的模擬分析系統的時域反應,在本論文中利用行為模型模擬系統的時域反應,可以大幅減少模擬的時間。控制電路利用0.6微米的互補式金氧半導體積體電路技術來實現,包含輸入輸出接腳的面積為1.8乘1.8毫米平方。當輸出電流由2安培增加至20安培時,輸出電壓最多降低150毫伏,並於100微秒內回到靜態容忍的界線內,大電流暫態反應符合嚴格的電源需求,並且與模擬的結果相符。
Several high performance controllers for switching-mode DC–DC converter are proposed. In order to achieve fast transient response, high efficiency, stable operation, and low switching noise, analysis and circuit design of the controllers are comprehensively investigated in this dissertation. Controllers are realized by CMOS analog and digital mixed-mode integrated circuits techniques.

Free-running control is the simplest among all control topologies of switching power supply. However, the switching frequency depends on the operating conditions and power filters. Thus, the use is limited in noise sensitive devices. Besides, only few related literatures provide analytical insights into this kind of control. Two common free-running control topologies, ripple control and constant on-time control, are investigated. Circuits architectures are proposed to improve these controllers.
Switching frequency of the constant on-time regulator can be also stabilized by adjusting the on time according to input and output voltages. Unstable operation of free-running control due to noise on feedback signal is discussed. A novel compensation circuit is proposed to improve the frequency response and noise immunity of constant on-time control. This compensation circuit uses a built-in integrator to generate a ramp signal to trigger the comparator. Therefore, it is less susceptible to noise. Stable operation and fast response are obtained. The proposed control circuits are realized in a 1 um CMOS technology with area of 5.2 mm^2 including the I/O pads. Experimental results showed fast response during load and line transients. Efficiency from 86 % to 93 % is obtained over a load range from 10 mA to 3 A under 5 V input voltage and 2.476 V output voltage. The load and line regulations are 0.032 %/A and 0.034 %/V that are superior to conventional current-mode and voltage-mode PWM control.

Switching frequency of the ripple control regulator can be synchronized by a novel method that uses a phase-locked loop to lock the switching signal with an input clock. Voltage-mode and current-mode control circuits are presented for the buck and boost power stages, respectively. Both steady-state response and small-signal model are discussed. Derived transfer functions are useful for designing the control loop and compensation network. By taking linearization of the relationship of switching frequency and delay, a linear model is obtained for loop parameter design and PLL stability analysis. The proposed regulators were simulated in transistor level using SPICE. Input voltage and output voltage are 20 V and 1.5 V respectively for the buck regulator. During the steady state, the switching frequency was locked at 300 kHz. Load regulation is 0.0046 %/A and line regulation is 0.028 %/V. Input voltage and output voltage are 2.4 V and 3.3 V respectively for the boost regulator. During the steady state, the switching frequency was locked at 300 kHz. Load regulation is 0.96 %/A and line regulation is 0.75 %/V. More simulation results are also shown in this dissertation.

Analog controllers are sensitive to noise, process, temperature and component variations. Tuning these controllers is quite complicated as well. The uses of digital controllers are limited by their complex circuits and higher cost. In this thesis, the proportional current feedback technique is proposed to accelerate transient response of the voltage-mode switching regulators. With this technique, the complexity of analog-to-digital conversion circuits and digital computation circuits is greatly reduced. Performance can be easily tuned by adjusting the parameters. Instead of transistor-level simulation, a Matlab behavior model is build to simulate time-domain system response. Fast and accurate results can be obtained from this model. The proposed control circuits are realized in a 0.6 um CMOS technology with area of 1.8×1.8 mm^2 including the I/O pads. Experimental results showed the output voltage dropped 150 mV and recovered to static tolerance in 100 us during a load transient from 2 A to 20 A. The performance of the regulator met strict requirements and verified the simulation results.
中文摘要 i
English Abstract v
誌謝 ix
Table of Contents xi
List of Tables xv
List of Figures xvii
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Trends and Challenges of Power Supply Design in Microelectronic Era . . . 3
1.2.1 High e±ciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Low output voltage, low noise . . . . . . . . . . . . . . . . . . . . . 4
1.2.3 Compact size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.4 Fast transient response . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.5 Wide duty ratio range . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.6 Digital control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Research Goals and Contribution . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Switching Regulator Basics 11
2.1 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.2 Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Modulation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . 14
2.2.2 Pulse-Skipping Modulation (PSM) . . . . . . . . . . . . . . . . . . 14
2.2.3 Pulse-Frequency Modulation (PFM) . . . . . . . . . . . . . . . . . 15
2.3 Basic Converter Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 E±ciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.2 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.3 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.4 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.5 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . 21
3 A Compact Digital Buck Controller with Proportional Current Feedback 23
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Digital Control for Switching-Mode DC-DC Converter . . . . . . . . . . . 24
3.3 Proportional Current Feedback . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Voltage-Mode and Current-Mode Control . . . . . . . . . . . . . . . 25
3.3.2 Converter Load Transient Response . . . . . . . . . . . . . . . . . . 28
3.3.3 Control Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.1 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.2 Digital Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5 Time Domain System Modelling and Simulation . . . . . . . . . . . . . . . 40
3.5.1 Behavior Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.5.2 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6 Experiment Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 A Frequency Stabilized Constant On-Time Controller with Low Noise
Susceptibility 51
4.1 Constant On-time control and Frequency Stabilization Technique . . . . . 52
4.2 Stability Issues of Free-Running Control . . . . . . . . . . . . . . . . . . . 54
4.2.1 Noise induced instability . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.2 Loop gain of free-running regulator . . . . . . . . . . . . . . . . . . 55
4.3 Compensation and Circuits Implementation . . . . . . . . . . . . . . . . . 60
4.3.1 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3.2 Timing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.3 Regulator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.4 Simulation and Experiment Results . . . . . . . . . . . . . . . . . . . . . . 71
4.4.1 Steady State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.4.2 Load Transient Response . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4.3 Line Transient Response . . . . . . . . . . . . . . . . . . . . . . . . 78
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5 Frequency Synchronized Ripple Controllers 83
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2 Voltage-Mode Ripple Control Buck Regulator with Fixed Output Frequency
84
5.2.1 Voltage-Mode Ripple Control Buck Regulators . . . . . . . . . . . . 84
5.2.2 Circuit Design for Fixed Switching Frequency . . . . . . . . . . . . 86
5.2.3 Phase-Locked Loop Analysis . . . . . . . . . . . . . . . . . . . . . . 93
5.2.4 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.2.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3 Current Mode Ripple Control Boost Regulator with Fixed Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.1 Boost Converter Steady-State Analysis . . . . . . . . . . . . . . . . 114
5.3.2 Boost Converter Small-Signal Analysis . . . . . . . . . . . . . . . . 119
5.3.3 Current-Mode Ripple Control Boost Converter . . . . . . . . . . . . 124
5.3.4 Circuit Design for Fixed Switching Frequency . . . . . . . . . . . . 126
5.3.5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3.6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6 Conclusions and Future Works 145
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Bibliography 149
簡歷 161
Publication List 163
[1] "MAX1714 high-speed step-down controller for notebook computers," Datasheet, Maxim Integrated Products, 1999.
[2] H. W. Whittington, B. W. Flynn, and D. E. Macpherson, Switched Mode Power Supplies - Design and Construction. Research Studies Press Inc., 1997.
[3] K. K. Sum, Switch Mode Power Conversion --- Basic Theory and Design. NewYork: Marcel Dekker, 1984.
[4] M. Brown, Power Supply Cookbook. Newton, MA: Butterworth-Heinemann, 1994.
[5] C. Basso, Switch-Mode Power Supply Spice Cookbook. New York: McGraw-Hill, 2001.
[6] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed.Dordrecht, the Netherlands: Kluwer Academic Publishers, 2001.
[7] A. I. Pressman, Switching Power Supply Design, 2nd ed. McGraw-Hill, 1998.
[8] D. Monticelli, “System approaches to power management," in Proc. IEEE APEC, vol. 1, Mar. 2002, pp. 3-7.
[9] J. Doyle and B. Broach, “Power optimization challenges in next-generation handsets," National Semiconductor.
[10] “Cell phone power system management," ON Semiconductor, June 2004.
[11] A. P. Dancy, R. Amirtharajah, and A. P. Chandrakasan, “High-efficiency multiple-output DC-DC conversion for low-voltage systems," IEEE Trans. VLSI Syst., vol. 8, no. 3, pp. 252-263, June 2000.
[12] “Voltage regulator-down VRD 10.0 design guide," Intel Corp., 2004.
[13] L. Geng, Z. Chen, and J. Liu, “Design of a hybrid monolithic integrated switched capacitor DC-DC step-up converter," in Proc. IEEE Power Electronics and Motion Control Conference, vol. 1, Aug. 2000, pp. 263-266.
[14] V. Mehrotra, J. Sun, and S. Chandrasekaran, “Ultra compact DC-DC converters for the digital age," in Proc. IEEE IECON, vol. 4, Nov. 2002, pp. 3232-3237.
[15] H. Wetzel, N. Frohleke, F. Meier, and P. Ide, “Comparison of low voltage topologies for voltage regulator modules," in Proc. IEEE Industry Applications Conference, vol. 2, Oct. 2002, pp. 1323-1329.
[16] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor," IEEE Trans. VLSI Syst., vol. 11, no. 3, pp. 514-522, June 2003.
[17] V. Kursun, S. G. Narendram, V. K. De, and E. G. Friedman, “Low-voltage-swing monolithic dc-dc conversion," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 5, pp. 241-248, May 2004.
[18] G. Patounakis, Y. W. Li, and K. L. Shepard, “A fully integrated on-chip DC-DC conversion and power management system," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 443-451, Mar. 2004.
[19] X. Zhou, P.-L. Wong, P. Xu, F. C. Lee, and A. Q. Huang, “Investigation of candidate VRM topologies for future microprocessors," IEEE Trans. Power Electron., vol. 15, pp. 1172-1182, Nov. 2000.
[20] B. Arbetter and D. Maksimovic, “DC-DC converter with fast transient response and high e±ciency for low-voltage microprocessor loads," in Proc. IEEE APEC, vol. 1, Feb. 1998, pp. 156-162.
[21] P.-L. Wong, F. C. Lee, X. Zhou, and J. Chen, “VRM transient study and output ‾lter design for future processors," in Proc. IEEE IECON, vol. 1, Aug. 1998, pp. 410-415.
[22] Y.-Y. Tzou, “Design of switching power supplies," Seminar material, Intelligent Power Module Integrated Design Lab., Apr. 2004.
[23] Y. Panov and M. M. Jovanovic, “Design and performance evaluation of low-voltage/high-current DC/DC on-board modules," IEEE Trans. Power Electron., vol. 16, no. 1, pp. 26-33, Jan. 2001.
[24] C. K. Tse and C. Y. Tam, “A quasi-linear controller for DC/DC converter using a TMS320 digital signal processor," in Proc. IEEE PESC, vol. 2, 1994, pp. 1040-1045.
[25] A. M. Wu, J. X. Xiao, D. Markovic, and S. R. Sanders, “Digital PWM control: Application in voltage regulation modules," in Proc. IEEE PESC, vol. 1, 1999, pp. 77-83.
[26] J. A. Abu-Qahouq, N. Pongratananukul, I. Batarseh, and T. Kasparis, “Multiphase voltage-mode hysteretic controlled VRM with DSP control and novel current sharing," in IEEE Applied Power Electronics Conference and Exposition, vol. 2, 2002, pp. 663-669.
[27] T. W. Martin and S. S. Ang, “Digital control for switching converters," in Proc. IEEE Int. Symp. Ind. Electron., 1995, pp. 480-484.
[28] Y. Duan and H. Jin, “Digital controller design for switchmode power converters," in Proc. IEEE APEC, vol. 2, Mar. 1999, pp. 967-973.
[29] G. M. Cooley, T. S. Fiez, and B. Buchanan, “PWM and PCM techniques for control of digitally programmable switching power supplies," in Proc. IEEE ISCAS, vol. 2, Apr. 1995, pp. 1114-1117.
[30] A. Prodic, D. Maksimovic, and R. W. Erickson, “Design and implementation of a digital PWM controller for a high-frequency switching DC-DC power converter," in Proc. IEEE IECON, vol. 2, Nov. 2001, pp. 893-898.
[31] Z. Lu, Z. Qian, Y. Zeng, W. Yao, G. Chen, and Y. Wang, “Reduction of digital PWM limit ring with novel control algorithm," in Proc. IEEE APEC, vol. 1, Mar. 2001, pp.
4-8.
[32] A. Dancy and A. Chandrakasan, “A reconfigurable dual output low power digital PWM power converter," in Proc. IEEE International Symposium on Low Power Electronics and Design, Aug. 1998, pp. 191-196.
[33] C.-H. Tso and J.-C. Wu, “An integrated digital PWM DC/DC converter," in Proc. IEEE ICECS, vol. 1, 2000, pp. 104-107.
[34] ||, “An integrated digital PWM DC/DC converter using proportional current feedback," in Proc. IEEE ISCAS, vol. 3, 2001, pp. 65-68.
[35] ||, “Analysis and implementation of proportional current feedback technique for digital PWM DC-DC converters," IEICE Transactions, vol. E86-C, no. 11, pp. 2300-2308, Nov. 2003.
[36] A. V. Peterchev and S. R. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters," IEEE Trans. Power Electron., vol. 18, no. 1,
pp. 301-308, Jan. 2003.
[37] S. Saggini, M. Ghioni, and A. Geraci, “An innovative digital control architecture for low-voltage, high-current DC-DC converters with tight voltage regulation," IEEE Trans. Power Electron., vol. 19, no. 1, pp. 210-218, Jan. 2004.
[38] C. W. Deisch, “Simple switching control method changes power converter into a current source," in IEEE Power Electron. Specialists Conf., 1978, pp. 300-306.
[39] R. Redl and N. O. Sokal, “Current-mode control, five different types, used with the three basic classes of power converters: Small-signal ac and large-signal dc characterization, stability requirements, and implementation of pratical circuits," in Proc. IEEE PESC, 1985, pp. 771-785.
[40] R. B. Ridley, “A new continuous-time model for current-mode control," IEEE Trans. Power Electron., vol. 6, no. 2, pp. 271-280, Apr. 1991.
[41] R. D. Middlebrook, “Modeling current-programmed buck and boost regulators," IEEE Trans. Power Electron., vol. 4, no. 1, pp. 36-52, Jan. 1989.
[42] “Modelling, analysis and compensation of the current-mode converter," Application Note U-97, Texas Instruments, 1999.
[43] L. Dixon, “Average current mode control of switching power supplies," Application Note U-140, Texas Instruments, 1999.
[44] R. B. Ridley, “Current mode or voltage mode?" Switching Power Magazine, vol. 1, no. 2, pp. 4,5,9, Oct. 2000.
[45] R. Mammano, “Switching power supply topology --- voltage mode vs. current mode,"
Application Note DN-62, Texas Instruments, 1994.
[46] R. Redl, “Small-signal high-frequency analysis of the free-running current-mode-controlled converters," in Proc. IEEE PESC, 1991, pp. 897-906.
[47] A. S. Kislovski, R. Redl, and N. O. Sokal, Dynamic Analysis of Switching-Mode DC/DC Converters. New York: Van Nostrand Reinhold, 1991.
[48] R. B. Ridley, “A new continuous-time model for current-mode control with constant
frequency, constant on-time, and constant o®-time, in CCM and DCM," in IEEE Power Electron. Specialists Conf., 1990, pp. 382-389.
[49] S.-S. Hong and B. Choi, “Technique for developing averaged duty ratio model for DC-DC converters employing constant on-time control," IEE Electronics Letters,
vol. 36, no. 5, pp. 397-399, Mar. 2000.
[50] J. Sun, “Small-signal modeling of variable-frequency pulsewidth modulators," IEEE Trans. Aerosp. Electron. Syst., vol. 38, pp. 1104-1108, July 2002.
[51] R. Redl and N. O. Sokal, “Frequency stabilization and synchronization of free-running current-mode-controlled converters," in Proc. IEEE PESC, 1986, pp. 591-530.
[52] G. W.Wester, “Describing-function analysis of a ripple regulator with slew-rate limits and time delays," in IEEE Power Electron. Specialists Conf., 1990, pp. 341-346.
[53] W. Gu, W. Qiu, W. Wu, and I. Batarseh, “A multiphase DC/DC converter with hysteretic voltage control and current sharing," in IEEE Applied Power Electronics
Conference and Exposition, vol. 2, 2002, pp. 670-674.
[54] S.-C. Wong and Y.-S. Lee, “Spice modeling and simulation of hysteretic current-controlled cuk converter," IEEE Trans. Power Electron., vol. 8, no. 4, pp. 580-87,
Oct. 1993.
[55] Y. F. Liu and C. Sen, “Large-signal modeling of hysteretic current-programmed converters," IEEE Trans. Power Electron., vol. 11, pp. 423-430, May 1996.
[56] “Designing fast response synchronous buck regulators using the TPS5210," Application Report, Texas Instruments, Mar. 1999.
[57] R. Miftakhutdinov, “Analysis and optimization of synchronous buck converter at high slew-rate load current transients," in Proc. IEEE PESC, 2000, pp. 714-720.
[58] “Introduction to power supplies," Application Note 556, National Semiconductor Corp., Sept. 2002.
[59] “DC-DC converter tutorial," Application Note 710, Maxim Integrated Products, Oct. 2000.
[60] “Building a power supply that works," Application Note Number APP1897, Maxim Integrated Products, Feb. 2003.
[61] K. H. White, D. R. Lampe, F. C. Blaha, and I. A. Mack, “Characterization of surface channel CCD image arrays at low light levels," IEEE J. Solid-State Circuits, vol. 9,
pp. 1-12, Feb. 1974.
[62] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,"
Proc. IEEE, vol. 84, pp. 1584-1614, Nov. 1996.
[63] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic capacitance matching errors and corrective layout procedures," IEEE J. Solid-State Circuits, vol. 29, pp. 611-616, May 1994.
[64] G. Wei and M. Horowitz, “A low power switching power supply for self-clocked systems," in Proc. IEEE/ACM International Symposium on Low Power Electronics and Design, 1996, pp. 313-317.
[65] R. D. Middlebrook, “Measurement of loop gain in feedback system," International
J. of Electronics, vol. 38, pp. 485-512, Apr. 1975.
[66] B. H. Cho and F. C. Lee, “Measurement of loop gain with the digital modulator," in Proc. IEEE PESC, 1984, pp. 363-373.
[67] K. M. Smedley and S. Cuk, “One-cycle control of switching converters," in Proc. IEEE PESC, vol. 10, Nov. 1991, pp. 888-896.
[68] P. Midya, M. F. Greuel, and P. T. Krein, “Sensorless current mode control|an observer-based technique for DC-DC converters," in IEEE Power Electron. Specialists Conf., vol. 1, 1997, pp. 197-202.
[69] J. T. Mossoba and P. T. Krein, “Design and control of sensorless current mode DC-DC converters," in IEEE Applied Power Electronics Conference and Exposition, vol. 1, 2003, pp. 315-321.
[70] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. New York: McGraw-Hill, 2001.
[71] P. Larsson, “A 2-1600-MHz CMOS clock recovery PLL with low-V dd capability," IEEE J. Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999.
[72] B. Razavi, RF Microelectronics, 1st ed. Upper Saddle River, NJ: Prentice Hall PTR, 1997.
[73] D. Banerjee, PLL Performance, Simulation, and Design, 3rd ed. Dean Banerjee Pubns, 2003.
[74] R. E. Best, Phase-Locked Loops : Design, Simulation, and Applications, 5th ed. New York: McGraw-Hill, 2003.
[75] “Understanding boost power stages in switchmode power supplies,” Application Report Number SLVA061, Texas Instruments, Mar. 1999.
[76] R. D. Middlebrook and S. Cuk, “A general unified approach to modeling switching converter power stages," in Proc. IEEE PESC, 1976, pp. 18-34.
[77] V. Vorperian, R. Tymerski, and F. C. Lee, “Equivalent circuit models for resonant and PWM switches," IEEE Trans. Power Electron., vol. 4, pp. 205-214, Apr. 1989.
[78] V. Vorperian, “Simplified analysis of PWM converters using the model of the PWM switch: parts I and II," IEEE Trans. Aerosp. Electron. Syst., vol. AES-26, pp. 490-505, May 1990.
[79] C. Basso, “A tutorial introduction to simulating current mode power stages," PCIM Magzine, Oct. 1997.
[80] A. Capel, G. Ferrante, D. O'Sullivan, and A. Weinberg, “Application of the injected current model for the dynamic analysis of switching regulators with the new concept of LC3 modulator," in Proc. IEEE PESC, 1978, pp. 135-147.
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