臺灣博碩士論文加值系統

隨著系統晶片（SOC）的發展，持續降低互補式金氧半（CMOS）場效電晶體元件中的閘極介電層及非揮發性記憶體（non-volatile memories）中的複晶矽層間介電層（inter-poly dielectric）厚度以提高元件密度及降低操作電壓變得十分重要。為了滿足以上的需求並獲得較低的漏電流及較高的可靠度，利用高介電常數材料（high-�菕^來取代二氧化矽（SiO2）變成是不可或缺的趨勢。
本篇論文研究沉積後高溫退火（post-deposition annealing）溫度對有機金屬化學氣相沉積（metal organic chemical vapor deposition）之高介電常數材料三氧化二鋁（Al2O3）及二氧化鉿（HfO2）複晶矽層間電容的影響。實驗結果顯示，對三氧化二鋁及二氧化鉿複晶矽層間電容，不論是漏電流、電子捕捉率或崩潰電荷，900oC和800oC分別是最佳化條件。因此，等效氧化層厚度為5奈米及3奈米的三氧化二鋁和二氧化鉿將是45奈米及32奈米世代以下堆疊式快閃記憶體的絕佳候選複晶矽層間介電質。

For the system-on-chip (SOC) application, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPDs) for electrically-erasable programmable read-only-memory (EEPROM) and stacked-gate flash memory is needed to obtain high density and low operation voltage. To meet the above requirements and exhibit low leakage current as well as good reliability, the replacement of high-�� materials for SiO2 have become indispensable.
In this thesis, we investigated the effects of post-deposition annealing (PDA) temperature on the electrical properties and reliability characteristics of metal-organic chemical vapor deposition (MOCVD) aluminum oxide (Al2O3) and hafnium oxide (HfO2) inter-poly capacitors. For Al2O3 and HfO2 inter-poly capacitors, samples exhibit optimal quality in terms of leakage current, electron trapping rate and charge-to-breakdown (QBD) when annealed at 900oC and 800oC respectively. As thin as 5nm and 3nm equivalent oxide thickness (EOT) of Al2O3 and HfO2 IPD is suitable to meet the requirement of 45nm and 32nm generation stacked-gate flash memories respectively.

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