臺灣博碩士論文加值系統

本篇論文中，我們將探討和比較所製作的新穎結構，此新穎結構具有加厚的汲/源極和一個薄通道，因加厚的汲/源極和薄通道帶來的效應，我們可以增大導通狀態時的電流以及降低漏電流，進而改善我們的開/關電流的比值至107，且更可以抑制扭節現象 (kink effect) 的產生，而不需要在製程中多出一道額外的光罩。在我們的研究中，將新結構與傳統結構相比，開/關電流比在汲極電壓為5V時，將會從6*106增加到3.5*107。此新穎結構的各種尺寸也具備不錯的對稱性。此外我們還探討了閘極下方與汲/源極重疊處對元件特性的影響，我們認為此區較小會獲得較佳之電性。

In this thesis, the characteristics of the novel structure of poly-Si TFTs with thick S/D and thin channel have been investigated and compared. With the thick S/D and thin channel, we can not only decrease the off-state current but also increase the on-state current. Therefore, we succeed to achieve the on/off ratio about 7 orders and substantially suppress the kink effect without an extra mask. In our study, the on/off ratio is rose from 6*106 to 3.5*107 for Vds = 5V, W/L = 50 μm/10 μm. We also have a great symmetry for four device sizes of our novel structure of LTPS TFTs. In our experiment, we also investigated the influence of different gate-overlap region, we have shown the smaller gate-overlap region would be more better.

Reference

[1] T.Serilawa, S.shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility Poly-Si TFTs for large-area LCD’s,” IEEE Trans. Electron Dev., vol. 36, no. 9, pp. 1929,1989.
[2] S. Ikeda et al., “A polysilicon transistor technology for large capacity SRAMs,” IEDM Tech. Dig., pp. 469, 1990.
[3] F. Hayashi and M. Kitakata, “A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond, “ VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on, 1992, p36-37
[4] S. Morozumi et al., “Completely integrated contact-type linear image sensor,” IEEE Trans. Electron Devices., vol. 21, no. 8, p. 1546, 1985
[5] H. C. Lin et al., “Deposition and Device application of in situ Boron doped Polycrystalline SiGe Films Grown at Low Temperature,” J. Appl Phys., vol. 42, no. 9, pp. 835-837, 1993.
[6] Y. Hayashi et al., “A thermal printer head with CMOS thin-film transistor and heating elements integrated on a chip,” ESSCC Digest, pp. 266, 1988.
[7] N. Yamauchi, Y. Inaba, and M. Okamura, “An integrated photodetector amplifer using p-i-n photodiodes and poly-Si thin-film transistors,” IEEE Photonic Tec. Lett.,vol. 5, no. 3, p.319, 1993.
[8] H. C. Tuan, “Amorphous silicon thin film and its applications to large-area elements,” Master. Rec. Soc. Ump. Proc., vol. 33, p.247, 1984.
[9] J. R. Ayres and N. D. Young, “Hot carrier effects in devices and circuits formed from poly-Si,” IEEE proc. Circuits Devices Syst., vol. 131, no. 1, p.38, 1994.
[10] Tien-Fu Chen, Ching-Fa Yeh, and Jen-Chung Lou, “Investigation of Grain Boundary Control in the Drain Junction on Laser-Crystalized Poly-Si Thin Film Transistors,” IEEE Electron Device Lett., vol. 24, no. 7, 2003.
[11] A. Nakamura, F. Emoto, E. Fujii, and A, Tamamoto “A High-Reliability, Low-Operation-Voltage Monolithic Active-Matrix LCD by Using Advanced Solid-Phase growth Technique,” IEDM Tech. P.847, 1990.
[12] G. K. Giust and T. W. Sigmon, “Low-Temperature Polysilicon Thin-Film Transistors Fabricated from Laser-Processed Sputtered-Silicon Films,” IEEE Electron Device Lett., vol. 19, pp. 343-344, Sept. 1998.
[13] N. Kubo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, vol. 40, pp. 1876-1879, Oct. 1994.
[14] G. K. Giust and T. W. Sigmon, “High-Performance Laser-Processed Polysilicon Thin-Film Transistor,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 77-79, Feb. 1999.
[15] Won Kyu Kwak, Bong Rae Cho, Soo Young Yoon, Seong Jin Park, And Jin Jang, “A High Performance Thin-Film Transistor Using a Low Temperature Poly-Si by Silicide Mediated Crystallization,” IEEE Electron Device Lett., vol. 21, no. 3 March 2000.
[16] Seok-Woon Lee, Tae-Hyung Ihn, and Seung-Ki Joo, “Fabrication of High-Mobility P-Channel Poly-Si Thin Film Transistors by Self-Aligned Metal-Induced Lateral Crystallization,” IEEE Electron Device Lett., vol. 17, no. 8 Aug. 1996.
[17] Zhiguo Meng, Mingxiang Wang, and Man Wong, Member, IEEE, “High Performance Low Temperature Metal-Induced Unilaterally Crystallized polycrystalline Silicon Thin Film transistors for System-on-Panel Application,” IEEE Trans. Electron Devices, vol. 47, no. 2, Feb. 2000.
[18] Eric Campo, Emmanuel Scheid, Danielle Bielle-Daspet, and Jean-Paul Guillemet, “Influence of Rapid Thermal and Low Temperature Processing on the Electrical Properties of Polysilicon Thin Film Transistors,” IEEE Trans. On Semi. Manufacturing, vol. 8, no.3 Aug. 1995.
[19] Yong Woo Choi, Jeong O Lee, Tae Woong Jang, and Byung Tae Ahn, “Thin-Film Transistors Fabricated with Poly-Si Films Crystallized at Low Temperature by Microwave Annealing,” IEEE Electron Device Lett., vol. 20, no. 1, pp. 2-4, Jan. 1999.
[20] K. Tanaka, H. Arai, and S. Kohda, “Characteristics of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett., vol. 9, pp. 23-25, 1988.
[21] B. H. Min, C. M. Park, and M. K. Han, “A novel offset gated polysilicon thin film transistor without an additional offset mask,” IEEE Electron Device Lett., vol. 16, pp. 161-163, 1995.
[22] Yasuyoshi Mishima and Yoshiki Ebiko, “Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” IEEE Trans. Electron Devices, vol. 49, pp. 981-985, 2002.
[23] M. Hatano, H. Akimoto, and T. Sakai, “A novel self-aligned gate-overlapped LDD poly-Si TFT with high reliability and performance,” in IEDM Tech. Dig., 1997, pp. 523-526.
[24] Kwon-Young Choi, Jong-Wook Lee, and Min-Koo Han, “Gate-overlapped lightly doped drain poly-Si thin film transistors for large area-AMLCD,” IEEE Trans. Electron Devices, vol. 45, pp. 1272-1279, 1998.
[25] Byung-Hyuk Min and Jerzy Kanicki, “Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment,” IEEE Electron Device Lett., vol. 20, pp. 335-337, 1999.
[26] Shengdong Zhang, Ruqi Han, and Mansun J. Chan, “A novel self-aligned bottom gate poly-Si TFT with in-situ LDD,” IEEE Electron Devices Lett., vol. 22, pp. 393-395, 2001.
[27] In-Hyuk Song; Su-Hyuk Kang; Woo-Jin Nam; Min-Koo Han;
Electron Device Letters, IEEE, “A high-performance multichannel dual-gate poly-Si TFT fabricated by excimer laser irradiation on a floating a-Si thin film”.
[28] I. W. Wu, T. Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Devices Lett., vol. 12, no.4, p. 181, 1991.
[29] J. Jang, J. Y. Oh, and S. K. Kim, “Electric-field-enhanced crystallization of amorphous silicon,” Nature, vol.395, no.6701, pp.481-483, 1998.
[30] K.C.Park, K. Y. Choi,J. S. Y, and M. K. Han, “A new poly-Si thin fulm transistor with poly-Si/a-Si double active layer,” IEEE Electron Device Lett., vol.21, pp.488-490, Oct. 2000.
[31] K. R. Olasupo, M. K. Hatalis, “Leakage current mechanism in sub-micron polysilicon thin-film transistors,” in IEDM Tech. Dig., 1993, pp. 385-388

[32] T. Naguchi, H. Hayashi, and T. Oshima, “Low temperature polysilicon super-thin-fulm transistor (LSFT),” Jpn. J. Appl. Phys, vol.25, no.2, p.L121, 1986.
[33] M. Miyasaka, T. Komatsu, W. Itoh, A. Yamaguchi, and H. Ohashima, “Effects of channel thickness on poly-crystalline silicon thin film transistors,” Ext. Abstr. SSDM, 1995, pp.647-650.
[34] S. Yamada, S. Yokoyama, and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT,” in IEDM Tech. Dig., 1990, pp. 859-862
[35] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s” IEEE Trans. Electron Devices, vol. 37, pp. 2015-2021, Sept. 1990.
[36] J. G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banarjee, “Anomalous leakage current in LPCVD polysilicon MOSFET’s” IEEE Trans. Electron Devices, vol. ED-32, pp. 1878-1884, Sept. 1985.
[37] K. R. Olasupo and M. K. Hatalis, “Leakage current mechanism in sub-micron polysilicon thin film transistor,” IEEE Trans. Electron Devices, vol. 43 pp. 1218-1223, Aug. 1996.
[38] S. Yamada, S. Yokoyama, and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in Poly-Si TFT,” in IEDM Tech. Dig., 100-, pp. 859-862.
[39] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori,” Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s.” IEEE Trans. Electron Devices, vol. 37, pp.2015-2021, Sept. 1990.
[40] A. G. Lewis, T. Y. Huang, R. H. Bruce, M. Koyanagi, A. Chiang, and I. W. Wu,” Polysilicon thin film transistor for analogue circuit applications,” in IEDM Tech. Dig., 1988, pp. 264-267.
[41] M. Koyanagi, H. Kurino, T. Hasimoto, H. Mori, K. Hata, y. Hiruma, T. Fujimori, I. W. Wu, and A. G. Lewis, “Relation between hot-carrier light emission and kink effect in Poly-Si thin film transistors,” in IEDM Tech. Dig., 1991, pp. 571-574
[42] A. Kumar K.P. and J. K. O Sin, “Influence of lateral electric field on the anomalous leakage current in polysilicon TFT,” IEEE Electron Device Lett., to be published.
[43] Dieter K. Schroder, “Semiconductor Material and Device Characterization,” Wiley-INTERSCIENCE, 1998.