跳到主要內容

臺灣博碩士論文加值系統

(44.222.64.76) 您好!臺灣時間:2024/06/14 03:10
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:林世民
研究生(外文):Shih-Min Lin
論文名稱:利用改良式暫存器交換技巧設計追溯式維特比解碼器
論文名稱(外文):Design of an Efficient Traceback-Based Viterbi Decoder Using Modified Register-Exchange Technique
指導教授:陳紹基陳紹基引用關係
指導教授(外文):Sau-Gee Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:72
中文關鍵詞:維特比解碼器迴旋碼
外文關鍵詞:Viterbi decoderConvolutional codetraceback
相關次數:
  • 被引用被引用:0
  • 點閱點閱:310
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
迴旋碼是一種通道編碼,其經常被運用於數位通訊系統當中以降低資料傳輸的錯誤率。本論文討論了各種加-比較-選擇運算單元(add-compare-select units)的特色及其優缺點。又,在維特比解碼器架構中,實現殘存路徑解碼的方法計有兩大類:一為暫存器交換法(register-exchange approach),另一為追溯法(trace-back approach)。而本論文針對三種暫存器交換法進行模擬;另外,相較暫存器交換法而言,追溯法所耗功率較低。在2004年,Han暨多位學者利用暫存器交換的觀念實現一個以追溯法為基礎的維特比解碼器,此方法大大地降低功率耗損以及硬體複雜度。奠基於此研究,我們進一步改進Han等學者所提出之方法。依研究結果顯示,本研究所提出的方法不僅使得功率耗損益加改善,並裨益減少晶片面積,其降低的幅度相較於Han而言,分別達9%及4%。
Convolutional code is a widely used technique in digital communication systems to reduce bit error rate. In this thesis, features, merits and demerits of several add-compare-select units (ACSUs) are discussed. Further, in the architecture of Viterbi decoder, there are two categories of survivor memory units (SMUs): register-exchange approaches and trace-back approaches. We conduct simulations of three register-exchange approaches. Moreover, trace-back approaches consume significantly less power than register-exchange ones. In 2004, Han et al. proposed a new traceback-based Viterbi decoder using modified register-exchange schemes. This approach compared to traditional trace-back approaches is good for decreasing power dissipation and silicon area. Based on Han’s approach, we further propose a modified approach. According to simulation results, our approach achieves 9% and 4% improvement in power dissipation and silicon area respectively.
Contents
Chinese Abstract Ⅰ
English Abstract Ⅱ
Acknowledgement Ⅲ
Contents Ⅳ
List of Tables Ⅵ
List of Figures Ⅶ


Chapter 1 Introduction 1
1.1 Overview of FEC Coding in the Communication System 1
1.2 Motivation 2
1.3 Organization of the Thesis 3
Chapter 2 Convolutional Code and Viterbi Algorithm 4
2.1 Convolutional Code 4
2.1.1 Encoding of Convolutional Code 5
2.1.2 Trellis Diagram of Convolutional Code 7
2.2 Viterbi Algorithm 8
2.2.1 Maximum-Likelihood Decoding 8
2.2.2 Viterbi decoding algorithm 12
Chapter 3 Realizations of Viterbi Decoder 16
3.1 Branch Metric Unit 17
3.2 Add-Compare-Select Unit 19
3.2.1 Radix-2 ACS Structure 21
3.2.2 Radix-4 ACS Structure 22
3.2.3 Radix-2 CSAU Structure 26
3.2.4 Low-Power ACSU Structure 28
3.2.5 Comparisons of ACS Architectures 29
3.3 Path Metric Normalization 32
3.4 Find-State Unit 33
3.5 Survivor Memory Unit 34
3.5.1 Register-Exchange Approaches 35
3.5.1.1 Best State Approach 35
3.5.1.2 Fixed State Approach 36
3.5.1.3 Majority Vote Approach 38
3.5.1.4 Simulation Results of Register Exchange Approaches 39
3.5.2 Trace-Back Approaches 42
3.5.2.1 K-Pointer Trace-Back Approach 43
3.5.2.2 One-Pointer Trace-Back Approach 45
3.5.2.3 Hybrid K-Pointer and One-Pointer Approach 46
3.5.2.4 Trace-Back approach Using Modified Register-Exchange Schemes 48
Chapter 4 The Design of Proposed Viterbi Decoder 52
4.1 Proposed Efficient Viterbi Decoder Using Trace-Back Approach 52
4.2 Comparisons of Survivor Memory Unit Approaches 56
4.3 Simulation Results 60
4.4 VLSI Implementation of the Proposed Viterbi Decoder 62
4.5 Complexity and Power Consumption Evaluations of Viterbi Decoders 64
Chapter 5 Conclusions and Future Work 67
References 69
[1] A. J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. on Information Theory, Vol. IT-13, pp. 260-269, April 1967.
[2] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo Codes,” in Proc. Inter. Conf. Commun., pp. 1064-1070, May 1993.
[3] J. Han, T. Kim, and C. Lee, “High Performance Viterbi Decoder Using Modified Register Exchange Methods,” Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vol. 3, pp 553-556, May 2004.
[4] S. Haykin, Communication Systems, 4th Edition, John Wiley, 2001.
[5] G. D. Forney, “The Viterbi Algorithm,” Proceedings of the IEEE, Vol. 61, pp 268-278, March 1973.
[6] G. D. Forney, “Convolutional Codes II: Maximum Likelihood Decoding,” Information and Control, Vol. 25, pp. 222-226, July 1974.
[7] S. B. Wicker, Error Control Systems for Digital Communication and Storage, Prentice Hall, 1995.
[8] Y. Chang, H. Suzuki, and K. K. Parhi, “A 2-Mb/s 256-State 10-mW Rate-1.3 Viterbi Decoder,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, pp 826-834, June 2000.
[9] K. Page, and P. M. Chau, “Improved Architectures for the Add-Compare-Select Operation in Long Constraint Length Viterbi Decoding,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 1, pp. 151-155, January 1998.
[10] A. K. Yeung, and J. M. Rabaey, “A 210-Mb/s Radix-4 Bit-Level Pipelined Viterbi Decoder,” in IEEE Int. Solid-State Circuits Conference Dig. Tech. Papers, pp. 88-89, Feb. 1995.
[11] V. S. Gierenz, O. Weiß, T. G. Noll, I. Garew, J. Ashley, and R. Karabed, “A 550Mb/s Radix-4 Bit-Level Pipelined 16-State 0.25- CMOS Viterbi Decoder,” IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 195-201, July 2000.
[12] K. K. Parhi, “An Improved pipelined MSB-First Add-Compare Select Unit Structure for Viterbi Decoders,” IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 51, No. 3, pp. 504-511, March 2004.
[13] N. Bruel, E. Sicheneder, M. Loew, A. Schackow, J. Gliese, and C. Sauer, “A 2.8Gb/s, 32-State, Radix-4 Viterbi Decoder Add-Compare-Select Unit,” 2004 Symposium on VLSI Circuits Design of Technical Papers, pp. 170-173, June 2004.
[14] E. Yeo, S. A. Augsburger, W. R. Davis, and B. Nikolić, “A 500-Mb/s Soft-Output Viterbi Decoder,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, pp. 1234-1241, July 2003.
[15] G. Fettweis, R. Karabed, P. H. Siegel, and H. K. Thapar, “Reduced-Complexity Viterbi Detector Architectures for Partial Response Signaling,” in Proc. IEEE Global Telecommunications Conference, pp. 559-563, Nov. 1995.
[16] I. Lee, and J. L. Sonntag, “A New Architecture for the Fast Viterbi Algorithm,” IEEE Transactions on Communications, Vol. 51, No. 10, pp. 1624-1628, October 2003.
[17] M. Ghoneima, K. Sharaf, H. F. Ragai, and A. E. Zekry, “Low Power Units for the Viterbi Decoder,” Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Vol. 1, pp. 412- 415, August 2000.
[18] P. J. Black, and T. H. Meng, “A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp. 1877-1885, December 1992.
[19] A. M. Obeid, A. Garcia, M. Petrov, and M. Glesner, “A Multi-Path High Speed Viterbi Decoder,” ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on Electronics Circuits and Systems, Vol. 3, pp. 1160-1163, December 2003.
[20] G. Feygin, and P. G. Gulak, “Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders,” IEEE Transactions on Communications, Vol. 41, No. 3, pp. 425-429, March 1993.
[21] T. K. Truong, M. Shih, I. S. Reed, and E. H. Satorius, “A VLSI Design for a Trace-Back Viterbi Decoder,” IEEE Transactions on Communications, Vol. 40, No. 3, pp. 616-624, March 1992.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊