|
References
[1] R. G. Gallager, “Low-density parity-check codes,” Cambridge, MA: MIT Press, 1963. [2] D. J. C. Mackay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electron. Lett., Vol. 32, pp. 1645-1646, Aug. 1996. [3] T. J. Richardson and R. L. Urbabke, “Efficient encoding of low-density parity-check codes,” IEEE Trans. Inform. Theory, Vol. 47, pp. 638-656, Feb. 2001. [4] D. J. C. Mackay, S. T. Wilson, and M. C. Davey, “Comparison of constructions of irregular gallager codes,’’ IEEE Trans. Comm., Vol. 47, pp. 1449-1454, Oct. 1999. [5] S. J. Johnson and S. R. Weller, “A family of irregular LDPC codes with low encoding complexity,” IEEE Comm. Lett., Vol. 7, pp. 79-81, Feb. 2003. [6] M. C. Davey and D. J. C. Mackay, “Low-density parity-check codes over GF(q),” IEEE Comm. Lett., Vol. 2, pp. 165-167, Jun. 1998. [7] R. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inform. Theory, Vol. 27, pp. 533-547, Sep. 1981. [8] M. Luby, M. Mitzenmacher, A. Shokrollahi, D. Spielman, and V. Stemann, “Practical loss-resilient codes,” IEEE Trans. Inform. Theory, Vol. 47, pp. 569-584, Feb. 2001. [9] T. J. Richardson, M. A. Shokrollashi, and R. L. Urbanke, “Design of capacity-approaching irregular low-density parity-check codes,” IEEE Trans. Inform. Theory, Vol. 47, pp. 619-637, Feb. 2001. [10] D. J. C. Mackay, “Good error-correcting codes based on very sparse matrices,” IEEE Trans. Inform. Theory, Vol. 45, pp. 399-431, Mar. 1999. [11] F. R. Kschischang, B. J. Frey, and H. A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. Inform. Theory, Vol. 47, pp. 498-519, Feb. 2001. [12] H. Futaki and T. Ohtuski, “Low-density parity-check (LDPC) coded OFDM systems,” IEEE VTS, Vol. 1, pp. 82-86, Fall. 2001. [13] X. Y. Hu, E. Eleftheriou, D. M. Arnold, and A. Dholakia, “Efficient implementation of the sum-product algorithm for decoding LDPC codes,” IEEE GLOBECOM’01, Vol. 02, pp. 1036-1036E, Nov. 2001. [14] I. V. Kozintsev. Software for low-density parity-check codes. [Online] Available at: http://www.kozintsev.net/soft.html. [15] A. Nayagam. Software for low-density parity-check codes. [Online] Available at: http://arun-10.tripod.com/ldpc/ldpc.html. [16] Z. Wang, Y. Chen, and K. K. Parhi, “Area efficient decoding of quasi-cyclic low density parity check codes,” IEEE ICASSP’04, Vol. 5, pp. 49-52, May. 2004. [17] A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, Vol. 37, pp. 404-412, Mar. 2002. [18] Y. Chen and D. Hocevar, “A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder,” IEEE GLOBECOM’03, Vol. 3, pp. 113-117, Dec. 2003. [19]TGnSync, “TGnSync Proposal,” [Online] Available at: http://www.tgnsync.org/home.
|