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研究生:朱元志
研究生(外文):Yuan-Jih Chu
論文名稱:低密度對偶檢查碼結構之改進以及其解碼器之超大型積體電路實現
論文名稱(外文):An Improved LDPC Code Structure and Its VLSI Decoder Realization
指導教授:陳紹基陳紹基引用關係
指導教授(外文):Sau-Gee Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:81
中文關鍵詞:低密度對偶檢查碼差分集合
外文關鍵詞:LDPCdifference family
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  • 下載下載:43
  • 收藏至我的研究室書目清單書目收藏:0
由於低密度對偶檢查碼 (LDPC) 的編碼增益接近向農 (Shannon) 極限以及解碼程序上擁有低複雜度的特性,所以在近年來受到廣泛的討論。本文中,我們利用差分集合 (difference family) 的概念來建構一種新的低密度對偶檢查碼結構,此結構在編碼上擁有低複雜度的特性,以及在解碼器的設計上易於超大型積體電路 (VLSI) 實現。此外,在解碼器的設計上,我們使用部分平行 (semi-parallel) 的架構並使其平行度為10,設計一個碼率為3/4、長度為960位元、最大循環解碼次數為10的非規則低密度對偶檢查碼解碼器,在0.18 製程下,此解碼器之資料流為每秒370MHz、面積為80萬個邏輯閘、消耗功率為550mW。
In recent years, low-density parity-check (LDPC) codes have attracted a lot of attention due to the near Shannon limit coding gain when iteratively decoded. In this thesis, we construct a new structure of irregular LDPC codes based on using the difference families. The resulting codes can be encoded with low complexity and are suitable for the VLSI implementation of their decoder. With the semi-parallel architecture and a parallel factor of 10, an irregular LDPC decoder has been implemented, of which the code rate is 3/4, the code length is 960 bits, and the maximum number of decoding iterations is 10, respectively. The irregular LDPC decoder can achieve a data decoding throughput of up to 370Mbps, an area of 800k gate counts, and a power consumption of 550mW using the UMC 0.18 ASIC process technology.
中文摘要 Ⅰ
ABSTRACT Ⅱ
ACKNOWLEDGEMENT Ⅲ
CONTENTS Ⅳ
LIST OF TABLES Ⅵ
LIST OF FIGURES Ⅶ

Chapter 1 Introduction 1

Chapter 2 Low-Density Parity-Check Code 3
2.1 Fundamental Concept of LDPC Code 3
2.2 Code Construction 7
2.3 Encoding 10
2.4 Decoding 17
2.4.1 Decoding Procedure in One Iteration 18
2.4.2 Iterative Decoding Procedure 23
2.4.3 Efficient Check Node Computation 25

Chapter 3 A New Structure for Low-Density Parity-Check Code Using the Difference Family 33
3.1 The Difference Family 33
3.2 The Proposed Structure of LDPC Code 35

Chapter 4 Simulation Results 39
4.1 Floating-Point Simulations 42
4.2 Fixed-Point Simulations 46
4.2.1 Quantization of Initially Received Signal 46
4.2.2 Quantization of and 50
4.2.3 Summary of Fixed-Point Simulation Results 54

Chapter 5 VLSI Implementation of LDPC Decoder 56
5.1 Semi-parallel Decoder Architecture for the Proposed LDPC Codes 56
5.2 Architectures of the Check Node Function Unit and the Variable Node Function Unit 59

Chapter 6 Conclusion 76

References 78

Autobiography 81
References

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[13] X. Y. Hu, E. Eleftheriou, D. M. Arnold, and A. Dholakia, “Efficient implementation of the sum-product algorithm for decoding LDPC codes,” IEEE GLOBECOM’01, Vol. 02, pp. 1036-1036E, Nov. 2001.
[14] I. V. Kozintsev. Software for low-density parity-check codes. [Online] Available at: http://www.kozintsev.net/soft.html.
[15] A. Nayagam. Software for low-density parity-check codes. [Online] Available at: http://arun-10.tripod.com/ldpc/ldpc.html.
[16] Z. Wang, Y. Chen, and K. K. Parhi, “Area efficient decoding of quasi-cyclic low density parity check codes,” IEEE ICASSP’04, Vol. 5, pp. 49-52, May. 2004.
[17] A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, Vol. 37, pp. 404-412, Mar. 2002.
[18] Y. Chen and D. Hocevar, “A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder,” IEEE GLOBECOM’03, Vol. 3, pp. 113-117, Dec. 2003.
[19]TGnSync, “TGnSync Proposal,” [Online] Available at: http://www.tgnsync.org/home.
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