臺灣博碩士論文加值系統

DMT (Discrete multitone) 調變技術是目前絕大多數非對稱性用戶迴路 (ADSL)系統所採用的技術，在本論文中，我們首先提出一個觀念，利用增加取樣速度，提升原有非對稱性用戶迴路系統的傳輸速率至高速用戶迴路系統(VDSL)的範圍。 同時我們也提出一些演算法來降低信號相互干擾 (ISI)，以提升系統傳輸效能。
本論文主要分為三部分，第一部分是有關提升原有非對稱性用戶迴路系統的傳輸速率至高速用戶迴路系統的範圍，要達到這個目標，必須要提高使用頻寛。提高使用頻寛可從二方面進行，一是增大 FFT/IFFT尺寸，另一方面若維持FFT/IFFT 大小不變，則需要增加每一個次通道(sub-channel) 的頻寛，為了探討增加頻寛是否改變原有次通道的特性，即每一個次通道內訊號雜訊比變化不能過大，我們針對每一個次通道內訊號雜訊比變化由原本4 kHz 頻寛依序倍增到20 kHz進行分析，同時也針對在不同長度的電話線在各種干擾和雜訊的影響之下，此高速用戶迴路系統所能達到的最佳傳輸速率。
第二部分則是有關高速用戶迴路系統碼框定位的相關演算法，我們研究一種所謂低複雜度最大可能(low-complexity maximum likelihood)預測演算法，並加以改良，以適合高速用戶迴路系統使用。同時以數學推導証明我們改良的演算法比原有的效能好，因為它能找出傳送資料經過通道影響後真正的碼框起始點，原本的演算法則會因為通道效應影響，後移數個位置到通道強度高峰之處，造成所謂前置信號相互干擾 (precursor ISI)，影響接收端的信號雜訊比。用電腦模擬方式，也可以比較出兩種演算法在接收端的信號雜訊比，我們改良過的演算法表現較佳。
第三部分，我們引進一種以遞迴方式，減少殘餘信號相互干擾，降低接收端的數元錯誤率，如此可以減少兩組信號間的防護間隔 (guard interval)，甚至於可以完全不用防護間隔，可提高系統傳輸效能。

Discrete multitone (DMT) modulation is the technology selected for most ADSL systems. In this dissertation, we proposed a concept to upgrade this DMT-based ADSL system to the VDSL transmission data rate by increasing the sampling rate. We also proposed algorithms to improve the performance of this DMT-based VDSL system by minimizing the influence of inter-symbol interference (ISI).
This dissertation is divided into three parts. In the first part, we try to upgrade the transmission data rate of traditional DMT-based ADSL system to the VDSL range by raising the sampling rate. The sub-channel spacing will grow with the same ratio if the identical FFT is used. The sub-channel flatness and capacity for VDSL test loops are analyzed by varying the symbol rate from 4 kHz to 20 kHz. In this part, we also investigate the throughput of DMT-based VDSL system at high sampling rates under the influence of various noises/interferences. The throughput limitation of the VDSL system is discussed and the optimal solutions of the sampling rates under various test loop lengths and environment conditions are also investigated.
In the second part, a new modified low-complexity maximum likelihood (ML) algorithm for frame synchronization in discrete multitone VDSL transmission system is derived. Computer simulation results are included to show its improvement in Et/N0 of each tone in the received data. This algorithm estimates the frame boundary at the initial transition edge rather than at the middle peak of a shortened twisted-pair channel response. The timing margin degradation caused by precursor ISI can be reduced significantly, especially when the sub-channels are loaded with more bits.
In the third part, an iterative ISI cancellation algorithm is presented to improve the DMT-based VDSL system by canceling the residual ISI outside the guard interval recursively. The guard interval of the system can be shortened to raise the bandwidth efficiency. In addition, by some modifications, the BER performance can be improved significantly even without any guard interval.

CONTENTS
ABSTRACT I
LIST OF TABLES VIII
LIST OF FIGURES IX
GLOSSARY XI
CHAPTER 1 INTRODUCTION 1
1.1 DMT-BASED ADSL/VDSL SYSTEM ARCHITECTURE 5
1.2 TOPOLOGY OF VDSL TEST LOOP 10
CHAPTER 2 CHANNEL MODELING 12
2.1 TRANSMISSION-LINE RLCG CHARACTERIZATION 12
2.2 CONVERSION OF RLGC TO ABCD PARAMETERS 14
2.2.1 Two-Port Network and ABCD Parameters 14
2.2.2 ABCD Parameters of Multiple Sections and Bridged-taps 17
2.3 TRANSFER CHARACTERISTICS OF A SUBSCRIBER LOOP 19
2.4 SIMULATION RESULTS OF THE CHANNEL CHARACTERISTICS 20
2.5 INTERFERENCE AND NOISE MODELS 23
2.5.1 Crosstalk 23
2.5.2 Impulse Noise 27
2.5.3 Background Noise 28
CHAPTER 3 BIT LOADING AND OPTIMAL THROUGHPUT OF DMT-BASED VDSL SYSTEM 29
3.1 BIT LOADING CALCULATIONS 30
3.2 CHANNEL CAPACITY VS. SYMBOL RATE OR FFT SIZE 36
3.3 COMPUTER SIMULATIONS 39
3.3.1 Maximum Channel Capacity vs. Symbol Rate in AWGN Channel 39
3.3.2 AWGN vs. VDSL Noise 42
3.3.3 AWGN vs. Various Crosstalk 43
3.3.4 AWGN vs. Bridged-taps 45
3.3.5 Analysis of Maximum Throughput 46
3.4 SUMMARY 50
CHAPTER 4 FRAME SYNCHRONIZATION BY CYCLIC PREFIX 51
4.1 ML ALGORITHM FOR FRAME SYNCHRONIZATION 51
4.2 MODIFIED ML ALGORITHM 54
4.3 COMPUTER SIMULATIONS 57
4.3.1 Simulation Environment 57
4.3.2 Performance Comparison of ML and Modified ML Algorithms 59
4.3.3 Loop Length and Channel Characteristics 64
4.3.4 VDSL Test Loops with Complex Topologies 67
4.4 SUMMARY 69
CHAPTER 5 ISI CANCELLATION ALGORITHM FOR DMT-BASED VDSL SYSTEM 70
5.1 SYSTEM MODEL 71
5.1.1 DMT-based VDSL System 71
5.1.2 RISIC Algorithm 72
5.1.3 Kim’s Approach 74
5.1.4 IIC-ZP Algorithm 76
5.2 COMPUTER SIMULATIONS 77
5.2.1 Influence of the Residual ISI for a DMT-based System 77
5.2.2 Kim’s Approach and RISIC Performance in DMT-based VDSL System 81
5.2.3 Performance Comparison of IIC-ZP and RISIC Algorithms 83
5.2.4 Residual ISI and Symbol Error Rate 86
5.3 SUMMARY 91
CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 92
REFERENCES 95

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