臺灣博碩士論文加值系統

隨著互補式金氧半製程技術的發展，以及處理器運算能力的快速提昇，提示著用以傳輸資訊的寬頻資料連結越來越顯得需要。在許多的應用中，比如說電腦內部、電腦與電腦間和電腦與週邊間的介面，這樣的連結通常是一個很重要的部分。為了克服在資料傳輸過程中由各種雜訊源所導致的訊號完整性問題，接收器在整個高速連結效能的表現中扮演了一個重要的角色，而其中最複雜的部分就是資料回復電路的設計。傳統上，GaAs 和Si bipolar 等製程都較常被使用在這樣高速電路，然而，由於互補式金氧半製程本身低成本、低功率、高度整合的優勢，目前深次微米互補式金氧半製程也已經被考慮使用在這些高速電路。
論文主題在於使用標準互補式金氧半製程實現一個雙回路系統1.25Gb/s時脈資料回復電路。內容可分為五章，第一章為簡介，第二章以時脈資料回復電路的基本原理作為開始。然後，在設計系統參數的複雜取捨將被討論並且也討論所建議的架構工作原理，第三章描述使用一些電路可支援高效能、低成本、短的設計時間和可量測的設計與應用，此方法可符合1.25Gb/s 的輸入資料速率。第四章介紹超大型積體電路實行的注意事項，第五章總結此論文。

Table of the contents

Abstract(Chinese) i
Abstract(English) ii
Acknowledgement iv
Table of Contents v
List of Tables vii
List of Figures viii


Chapter 1 Introduction
1.1 Motivation 1
1.2 Fiber-Optic Transceiver 2
1.3 Data Format 3
1.4 Timing Margin Analysis 4
1.5 Thesis Overview 5
Chapter 2 Clock and Data Recovery Architectures
2.1 Principle of Operation 6
2.2 CDR Fundamental 8
2.2.1 Frequency Detector 9
2.2.2 Phase Detector 15
2.2.3 Voltage-Controlled Oscillator 16
2.2.4 Loop Filter 17
2.3 Loop Filter 18
2.3.1 Approximated Frequency Response with 1st-order RC lowpass filter 22
2.4 CDR Parameter Design 24
Chapter 3 A 1.25 Gb/s Clock and Data Recovery Design
3.1 Introduction 26
3.2 Circuit Description 26
3.2.1 Input and Output Interface 26
3.2.1.1 Preamplifier 27
3.2.1.2 Output Driver 30
3.2.2 Frequency Detector 31
3.2.3 Phase Detector 33
3.2.4 Charge Pump 35
3.2.4.1 Charge Pump 1 35
3.2.4.1 Charge Pump 2 37
3.2.5 Voltage Controlled Oscillator 39
3.2.5.1 The Fundamental of VCO 39
3.2.5.2 Practical Design 46
3.3 System Simulation Result 49

Chapter 4 VLSI Implementation
4.1 Layout 52
Chapter 5 Conclusion 55
Bibliography 57
Vita 61






List of Tables


Table 2-1 Logic table of the half-rate DQFD 14
Table 3-1 Comparison between LC-tank oscillator and ring oscillator 40
Table 4-1 Performance Summary 54






























List of Figures


Fig. 1-1 Typical Fiber-Optic Transceiver 2
Fig. 1-2 NRZ data 3
Fig. 1-3 Received Data Eye 5
Fig. 2-1 Half-rate CDR architecture 7
Fig. 2-2 A Data Regeneration (a) scheme, (b) timing diagram 8
Fig. 2-3 (a) Schematic of half-rate DQFD (b) Combinational logics 10
Fig. 2-4 State representation 11
Fig. 2-5 Timing diagram for (a) slow periodic data (b) fast periodic data 12
Fig. 2-6 A three-state logic of the half-rate DQFD 13
Fig. 2-7 Illustration of the VCO (a) model of the oscillator (b)characteristic 17
Fig. 2-8 A second-order low-pass filter 18
Fig. 2-9 Model of the CDR 19
Fig. 2-10 Bode plot of the open-loop transfer function 20
Fig. 2-11 Second-order bang-bang loop schematic 21
Fig. 2-12 The close-loop frequency response of the CDR 23
Fig. 2-13 The close-loop transient step response of a CDR 24
Fig. 3-1 Schematic of preamplifier 27
Fig. 3-2 Frequency response of the preamplifier 29
Fig. 3-3 Hysteresis window of the preamplifier 29
Fig. 3-4 The output of preamplifier with input of 27-1 PRBS 30
Fig. 3-5 Output Driver by the source follower 31
Fig. 3-6 Schematic of TSPC DFF 32
Fig. 3-7 Schematic of the XOR gate 32
Fig. 3-8 (a) Schematic of the phase detector (b) Phase Detector characteristics 34
Fig. 3-9 Schematic of the charge pump 1 35
Fig. 3-10 (a) Charge-pump suffering from charge sharing (Type A) (b) Charge removal transistors eliminate charge sharing (Type B) 36
Fig. 3-11 (a) Original current reuse topology (b) Final current reuse topology 38
Fig. 3-12 Schematic of the charge-pump 2 in this work 38
Fig. 3-13 Schematic of the four stages VCO and the delay cell 41
Fig 3-14 I-V curve of the symmetric load 41
Fig. 3-15 Schematic of self-biased replica-feedback bias generator 43
Fig. 3-16 Frequency response of the self-biased replica-feedback bias generator 44
Fig. 3-17 Schematic of differential-to-single-ended converter with 50% duty cycle 45
Fig. 3-18 Schematic of the delay cell with additional capacitive loads 46
Fig. 3-19 Schematic of linearization circuit 47
Fig. 3-20 Transfer curve of the linear circuit 47
Fig 3-21 The transfer curve of the VCO (a) without additional capacitive loads and linearization circuit (b) without linearization circuit (c) with both trimming circuits 49
Fig. 3-22 Acquisition process for initial fvco > desired frequency 50
Fig. 3-23 Acquisition process for initial fvco < desired frequency 50
Fig. 3-24 Retimed data and retimed clock 51
Fig. 3-25 jitter of the VCO output for input data with 27-1 PRBS 51
Fig. 4-1 Chip layout of the CDR 53

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