臺灣博碩士論文加值系統

此篇論文探討了三個電路設計，第一個部份探討高整合性多頻帶三角積分調變分數型頻率合成器電路設計，將802.11a/b/g無線網路系統與GSM/DCS1800手機系統的頻率合成器，利用50%除頻方法，將四個系統整合於單晶片中；頻率鎖定時間為30μs，相位雜訊-114dBc/Hz@1MHz，功率消耗105mW。第二部份探討802.11a整數型頻率合成器之設計，使用TSMC 0.25μm CMOS製程，設計一正交信號壓控震盪器，輸出頻率5.0~5.6GHz，相位雜訊-106Bc/Hz@1MHz。藉由設計吞波計數器（Pulse-Swallow Counter），將除數做程式化控制，除數範圍是516~534，以達成頻率合成的目的；同時使用4階迴路濾波器，鎖定時間40μs，相位邊際58度。第三部份則探討以8位元控制壓控震盪器輸出頻率之高解析度LC壓控震盪器設計，使用TSMC 0.18μm CMOS製程，藉由8組變容器，將壓控震盪器的輸出頻率解析度提高，並設計每個變容器的可調頻率範圍約4.67MHz，壓控震盪器的相位雜訊是-107dBc/Hz@1MHz。利用此電路，在配合高準確性的頻率檢測器，將可達成全數位化高頻頻率合成器之目的，可免去使用外掛的迴路濾波器，提高晶片整合度，並將鎖頻時間加快數倍以上。

In this thesis, we will discuss three circuit designs. In the first part, a high integration multi-bands ΣΔ fractional-N frequency synthesizer design is discussed. The 802.11a/b/g WLANs and GSM/DCS1800 mobile system frequency synthesizer are integrated in single chip by 50% frequency division technique. Frequency settling is 30μs. Phase Noise is -114dBc/Hz@1MHz. Total power consumption is 105mW. In the second, we discuss an 802.11a integer-N frequency synthesizer design. A quadrature voltage controlled oscillator is designed. The oscillation frequency ranges from 5.0GHz to 5.6GHz. Phase noise is -106Bc/Hz@1MHz. The pulse-swallow counter is used to program division number. Total division number is 516~534. Besides, the 4th order loop filter structure is adopted for low noise consideration. Frequency settling time is 40μs. Phase margin is 58degrees. In the third part, we will discuss a technique to increase voltage controlled oscillator frequency resolution by 8-bit varactors. The average varactor tuning range is designed to be about 4.67MHz. Phase noise is -107dBc/Hz@1MHz. With this high frequency resolution voltage controlled oscillator, and a high precision frequency detector, we can design a new all-digital frequency synthesizer. In this proposed structure, the loop filter is omitted, and chip integration is promoted. The frequency settling time is faster by several times.

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