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研究生:賴俊傑
研究生(外文):Jecy Lai
論文名稱:同步化單對線數位用戶迴路接收端之初始化時脈
論文名稱(外文):The Start-up Timing Recovery on Single-Pair High-Speed Digital Subscriber Line (SHDSL) Receiver
指導教授:紀翔峰
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:65
中文關鍵詞:時脈回復單對線數位用戶迴路
外文關鍵詞:timing recoverySHDSL
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本文主要藉由G994.1所規範的握持程序探討SHDSL時脈恢復工作,G994.1主要彈性地對各個不同xDSL的傳接器在初始化的程序統一規範。由於SHDSL使用單對銅線傳輸其載波頻率為單一頻率,為了實現此一傳輸協定之時脈恢復工作,我們提出以非線性產生光譜線無資料輔助的方式來作為同步化設計依據,設計的方式以純數位化的方式不需額外的控制電路調整真實時脈的取樣速度,我們所提出時脈復原的架構其中包含交織插補濾波器來做數位化重新取樣運算、前置濾波器過濾雜訊及降低取樣輸出速度、時脈誤差偵測器計算時脈誤差資訊、鎖相迴路抑制收斂時脈誤差的偏移。當完成時脈復原工作後,最後便是將G994.1傳輸資訊的內容解碼譯出成原始資料。
接收端於初始啟動階段要做時脈復原、等化器、迴響消除、相聲穿越等工作,主要分成前置啟動部份與啟動部份兩段,前置啟動部份主要藉由G994.1握持程序將系統的時脈粗調與相關的補償工作,此期間除需完成補償工作外時脈誤差必須在±50 ppm以內,到啟動部份進入資料模式必須將時脈鎖住到更小誤差範圍,此誤差範圍與補償工作影響重大,本文實際以C語言模擬定點實現方式,在完全不做任何補償工作的情況下,成功在前置啟動階段即完成時脈恢復工作達±50ppm誤差要求範圍內,若是要進一步改善時脈同步化的精確度可增加各端輸出位元,而時脈偏移率將可達到約±10ppm ,此一結果將有助於接收器分配更多的時間專注於調整補償工作。
We will confer the timing recovery of the SHDSL by the Recommendation G994.1 handshake procedure. This Recommendation provides a flexible mechanism for various Digital Subscriber Line (DSL) transceivers at the start-up procedure. SHDSL technology was available over a single pair copper line with single tone carrier frequency, for the implement of the timing recovery by the Recommendation, we provide architecture that base on the Non-linear Spectral Line method and non-data aided with all-digital way without additional control circuit adjusting the real clock timing. Including of Digital Interpolator for digitally resampling, Prefilter for filtering noise and downing the throughput, Timing Error Detector for computing the timing error information, Phase Lock Loop for the convergence of timing error offset. After achieving timing recovery, we will decode and recover G994.1 transmitting data.
Timing recovery, equalizer, echo canceller, crosstalk…etc are needed at the start-up procedure of the receiver. There are two major parts that are pre-activation and activation part. In the pre-activation part, the system of the timing clock should have coarse adjustment by the G994.1 procedure and fine compensations. During the period, not only the compensations will be well operated but the clock offset shall be within ±50ppm. After entering activation procedure and data mode, the clock offset should be locked in a small error range more. The compensation works will be deeply impact on the error range. In this thesis, the fixed-point implement was simulated on C language. Without doing any compensation, we successfully recover the timing error with the demand for ±50ppm clock offset range at the pre-activation process. With using more bits on each stage of the output, we can promote the accuracy of the clock and reduce its offset range to ±10ppm. The result will help receiver to have more time to do other compensation works.
中文摘要 i
英文摘要(English Abstract) iii
誌謝 v
目錄 vi

表目錄 ix
圖目錄 x

第一章 序論 1
1.1 DSL簡介 1
1.2 論文動機 6
1.3 論文組織 7

第二章 G994.1握持程序與規範(Handshake Procedure and specification) 8
2.1 系統簡介 8
2.2 信號與調變 10
2.2.1 信號種類 11
2.2.2 調變方式 12
2.3 接收端握持程序 13
2.4 SHDSL接收器所提出之握持程序架構 15

第三章 SHDSL接收器時脈復原之設計與G994.1之資料解碼(Data Decoder) 17
3.1 時脈復原之分類 17
3.2 產生光譜線之時脈同步器(Spectral Line Generating Clock Synchronizer) 20
3.3 時脈復原之系統架構 24
3.3.1 前置濾波器(Prefilter) 24
3.3.2 時脈誤差偵測器(Timing Error Detector) 25
3.3.3 鎖相迴路(Phase Lock Loop) 27
3.3.4 數位化重新取樣器之設計 28
3.3.4.1 重新取樣器之時脈迴路(Timing Loop) 28
3.3.4.2 交織插補方式(Interpolation Method) 29
3.4 G994.1調變之資料解譯 (Datum Decoding) 31

第四章 定點運算之實現 36
4.1 各參數定點表示式 36
4.1.1 插補端之實現(Interpolation Output Implementation) 36
4.1.2 平方器之實現(Squarer Output Implementation) 37
4.1.3 弦波乘法端之實現(Sinusoidal Multiplier Output Implementation) 38
4.1.4帶通濾波器端之實現 39
4.1.5平均動差(Moving Average)濾波端之實現 40
4.1.6取虛部信號端之實現 41
4.1.7迴路濾波器(Loop Filter)端之實現 42
4.1.8各輸出端之模擬比較圖 43

第五章 模擬結果與檢討 52
5.1通道模型與模擬參數 (Channel Model and Simulation Parameter) 52
5.1.1 通道模型 52
5.1.2 帶通濾波器 53
5.1.3平均動差濾波器(Moving Average Filter) 53
5.1.4迴路濾波器(Loop Filter) 54
5.2 結果與檢討 54

第六章 未來展望 63

參考文獻 65
[1] Peter Gysel and Dietrich Gilg “Timing Recovery in High Bit-Rate Transmission Systems Over Copper Pairs” IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO.12, DECEMBER 1998.
[2] Floyd M. Gardner, “Interpolation in Digital Modems – PART I: Fundamentals”IEEE TRANSACTIONS ON COMMUN., VOL. 41, NO. 3, pp. 501-507, March 1993.
[3] Floyd M. Gardner and Robert A. Harris, “Interpolation in Digital Modems – PART II: Implementation and Performance” IEEE TRANSACTIONS ON COMMUN., VOL. 41, NO. 6, pp. 998-1008, JUNE 1993.
[4] L. E. Franks, "Carrier and bit synchronization in data communication-A tutorial review," IEEE Trans. Communications, vol. COM-28, 11-7-1121, Aug. 1980.
[5] C.-P. JEREMY TZENG, DAVID A. HODGES AND DAVID G. MESSERSCHMIT,“Timing Recovery in Digital Subscriber Loops Using Baud-Rate Sampling” IEEE JOURNAL SELECTED AREAS IN COMMUN. VOL. SAC-4, NO. 8, pp. 1583-1586 NOVEMBER 1986.
[6] OSCAR AGAZZI, CHIN-PYNG JEREMY TZENG, DAVID G. MESSERSCHMIT AND DAVID A. HODGES, “Timing Recovery in Digital Subscriber Loops” IEEE TRANSACTIONS ON COMMUN. VOL. COM-33, NO. 6, pp.558-569 JUNE 1985.
[7] ITU-T G.991.2 (ex G.shdsl): Draft Recommendation
[8] ITU-T G994.1 Handshake procedures for Digital Subscriber Line (DSL) transceivers
[9] Heinrich Meyr, Marc Moeneclaey, Stefan A. Fechtel “Digital Communication Receivers - Synchronization, Channel Estimation and Signal Processing”
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