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研究生:陳育聖
研究生(外文):Yu-Sheng Chen
論文名稱:應用於無線個人通訊低功率分時帶通和差調變類比數位換器
論文名稱(外文):A Low Power Time Interleaved Band-pass Sigma Delta A/D Converter for Wireless Personal Communication
指導教授:董蘭榮董蘭榮引用關係
指導教授(外文):Lan-Rong Dung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:65
中文關鍵詞:和差調變器帶通類比數位轉換器分時系統
外文關鍵詞:sigma deltabandpass ADCtime interleaved
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帶通類比數位轉換器對電容的誤差以及高速度的處理上,面臨著對誤差極為靈敏,以及功率消耗極高的問題。因此我們採用了分時系統 (Time Interleaved System) 並且搭配上合成雜訊轉移函式 (NTF Synthesis) ,利用四個低通的三角積分 (ΔΣ) 類比數位轉換器合成一帶通類比數位轉換器。利用四個ADC的channel分時操作,每個一個ADC通道僅須操作在四分之一的帶通類比數位轉換器的工作頻率,如此一來除了可大幅降低ADC的功率消耗,延長電池的使用時間。此外,由於每一個ADC channel為一個single loop low-pass sigma delta ADC,此架構之ADC對於電容的不匹配,及OP DC gain的要求較為寬鬆不靈敏,因此我們亦可在設計電路上得到附加的好處,以及避免掉非理想效應及製程飄移所帶來的問題,以達到所求之解析度。
The thesis proposes a low power four path time-interlaeved sigma-delta modulator with switched-opamp technique for personal wireless communication applications, such as the GSM system. In this thesis, we design a time interleaved bandpass sigma delta modulator by using four channels with lowpass sigma delta modulator, and implement by TSMC.18 μm 1P6M CMOS models. And, to avoid gain and offset mismatch produce by each channel, additional reference channel calibrated the errors by off-chip digital calibration technique described in section 3.3. We implement the bnadpass A/D converter by low power technique and we overcome the non-ideal effect by off-chip calibration.
Chapter 1 Introduction ……………………………………………………………1
1.1 Motivation ………………………………………………………………1
1.2 Thesis Organization ………………………………………………………2
Chapter 2 Sigma Delta Modulator …………………………………………………3
2.1 The Basic Concept of Sigma Delta A/D Converter………………………3
2.1.1 Quantization Error ……………………………………………………3
2.1.2 Oversampling Technique………………………………………………6
2.1.3 Noise-Shaped Sigma-Delta Modulator……………………………9
2.2 The Lowpass Sigma Delta Modulator…………………………………12
2.2.1 First Order Lowpass Sigma Delta Modulator………………………12
2.2.2 Second Order Lowpass Sigma Delta Modulator……………………15
2.3 The Bandpass Sigma Delta Modulator …………………………………18
2.3.1 Transformation of the LP and BP Sigma Delta Modulator…………19
2.3.2 Second-Order Bandpass Sigma-Delta Modulator …………………21
2.3.3 Fourth-Order Bandpass Sigma-Delta Modulator …………………22
Chapter 3 Design of the Low-Power Bandpass Sigma-Delta Modulator ………25
3.1 Prototype of Switched-Capacitor Resonator………….…………………25
3.1.1 Resonator in Z-Domain………………………………………………25
3.1.2 Discrete-Time Resonator Topologies ..………………………27
3.1.3 The Design Challenge of Bandpass Sigma Delta Modulator..………29
3.2 Design A Time Interleaved Bandpass Sigma Delta ADC………………30
3.2.1 Time Interleaved System & Noise Transfer Function Synthesis……30
3.2.2 System level Design and Simulation of a Bandpass Modulator ….…32
3.3 Gain and Offset Calibration in Time Interleaved System………………36
3.3.1 The Gain and Offset Mismatch in Time Interleaved System………36
2.3.2 The Fully Digital Background Calibration….…………………37
Chapter 4 Implementation of Bandpass Sigma Delta Modulator ……………43
4.1 Block Diagram of Four Path Bandpass Modulator ….…………………43
4.1.1 Four Path Bandpass Modulator……………………………………43
4.1.2 Second Order Sigma Delta Modulator …....………………………44
4.2 Design and Simulation of Sub-Circuits…………………..………………46
4.2.1 Wide Swing Constant-Transconductance Bias Circuit…….……46
4.2.2 The Fully Differential Folded Cascode Operational Amplifier.. ….…48
4.2.3 Comparator…………………………………………………….……51
4.2.4 Clock Generator…………………………………………….. ….…53
4.3 Implementation and Simulation Report………………….………………54
4.3.1 Layout Flooplan and Layout Consideration………………….………54
4.3.2 Simulation Result of the Four Path Bandpass Modulator..………57
Chapter 5 Conclusions ……………....…………………………………………59
Reference ……………………………………………………………………………61
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