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研究生:古振杰
論文名稱:利用鎖相迴路模擬做NRZ訊號之相位偵測器的性能比較
論文名稱(外文):Performance Comparisons of Phase Detectors for NRZ Signals via Simulations of Phase-Locked Loops
指導教授:鄭木火
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:48
中文關鍵詞:相位偵測器頻率偵測器鎖相迴路
外文關鍵詞:Phase DetectorFrequency DetectorPhase-Locked Loops
相關次數:
  • 被引用被引用:3
  • 點閱點閱:468
  • 評分評分:
  • 下載下載:48
  • 收藏至我的研究室書目清單書目收藏:0
鎖相迴路(Phase-Locked Loops)的應用極為廣泛,已成為許多類比及數位系統的基本元件。在鎖相迴路架構中含有相位偵測器 (Phase Detector)、低通濾波器 (Low Pass Filter)及壓控振盪器(Voltage Controlled Oscillator)共三個功能方塊。其中相位偵測器的功能是用來比較壓控振盪器的輸出訊號與輸入訊號的相位差異。因此相位偵測器的特性常常是影響了整個鎖相迴路效能的關鍵方塊。由於在應用上大部份輸入為 NRZ (non-return to zero) 訊號,因此本論文針對使用在 NRZ信號常用的典型相位偵測器,Alexander相位偵測器及Hogge相位偵測器, 加以探討、分析、改進、及模擬。我們分別分析此二相位偵測器的工作原理及其特性,並比較其之間的優缺點;此外我們也就此二種相位偵測器,分別提出其改進的架構及實現電路以提昇其效能。本論文利用 MATLAB Simulink 的模擬環境下,建立一鎖相迴路的模擬系統以模擬在使用各種不同相位偵測器下,鎖相迴路系統的響應情形,並就其響應速度及穩態誤差加以探討比較。由於一系統在鎖相之前,必須先鎖頻。而常用方法是鎖相及鎖頻相互結合。因此本論文最後並就結合頻率偵測器 (Frequency Detector)的鎖相迴路系統, 探討及模擬在壓控振盪器時脈和 NRZ 訊號有初始頻率差時,鎖相迴路系統的響應。
A phase-locked loop (PLL) has been so widely used that it becomes a basic element in many modern digital or analog systems. A PLL consists of three functional blocks, namely, the phase detector (PD), the loop filter, and the voltage-controlled oscillator (VCO). The PD is used to detect the phase difference between the input signal and the oscillator output of the VCO; the performance of the PD often determines the performance of the PLL. In most
applications, the input signals are NRZ (non-return to zero) coded. Hence, in this thesis we focus on two most often used PDs for NRZ signals, the Alexander PD and the Hogge PD, for investigation,analysis, improvement and simulation. We first analyze the characteristics of these two PDs and discuss their differences, then we develop new block diagrams and circuit realizations for improving the PD
performances. We also develop a PLL simulation system using the Matlab Simulink to investigate the responses of PLL systems using various PDs; both the response time and the steady-state error are used for comparison and discussion. Since the frequency acquisition (frequency lock) is necessary before the phase lock and the most common realization is to combine the frequency detector with
the PD, we further embed the frequency detector into the PLL simulation system and investigate and simulate the response of the system under an initial frequency difference between the VCO output and input signals.
中文摘要.................................................i
英文摘要.................................................ii
誌謝.....................................................iii
圖目錄...................................................vi
表目錄 ..................................................ix
1. 緒論..................................................1
1.1 相位偵測器和頻率偵測器的簡介.........................1
1.2 研究目的與文獻回顧...................................1
1.3 論文架構.............................................2
2. Alexander相位偵測器及其改進...........................3
2.1 D型正反器之分析與模擬................................3
2.2 Alexander相位偵測器之分析與模擬......................5
2.3 Alexander相位偵測器改進型的架構及其模擬與討論.......................................................8
2.4 Alexander相位偵測器與其改進型及D型正反器之鎖相響應模擬討論.......................................................12
3. Hogge相位偵測器及其改進...............................16
3.1 Hogge相位偵測器之分析與模擬..........................16
3.2 Hogge相位偵測器改進型的架構及其模擬與討論............19
3.3 Hogge相位偵測器與其改進型之鎖相響應模擬討論..........20
3.3.1 使用Hogge相位偵測器的鎖相迴路之模組................23
3.3.2 模擬結果與比較討論.................................24
4. 結合相位偵測器及頻率偵測器之鎖相迴路模擬與比較........28
4.1 簡介.................................................28
4.2 頻率偵測器的分析與模擬...............................28
4.2.1 旋轉頻率偵測器的分析與模擬.........................29
4.2.2 使用旋轉頻率偵測器觀念的相位及頻率偵測器...........32
4.3 使用頻率偵測器達到鎖頻的模擬結果.....................34
4.3.1 旋轉頻率偵測器與相位及頻率偵測器的鎖頻比較.........34
4.3.2 使用旋轉頻率偵測器達到鎖頻的模擬結果...............40
5. 結論..................................................46
參考文獻.................................................47
[1]J.D.H. Alexander, "Clock Recovery from Random Binary Data," Elect. Lett., vol. 11, pp. 541-542, Oct. 1975.
[2]C.R. Hogge, "A Self-Correcting Clock Recovery Circuit,"
IEEE J.Lightwave Tech., Vol. 3, pp. 1312-1314, Dec. 1985.
[3]B. Lai and R.C. Walker, "A Monolithic 622 Mb/s Clock Extraction Data Retiming Circuit," in ISSCC Dig. Tech. Papers, pp. 144-145, Feb. 1991.
[4]J. Savoj and B. Razavi, "A 10-Gb/s CMOS Clock and
Data Recovery Circuit with a Half Rate Linear Phase
Detector," IEEE J. Solid-State Circuits, Vol. 36, pp. 761-768, May 2001.
[5]B. Razavi, Design of Analog Cmos Integrated Circuits, McGraw-Hill, 2001.
[6]A. Rezayee and K. Martin, "A 9-16Gb/s Clock and Data Recovery Circuit with Three-State Phase Detector and Dual-Path Loop Architecture," 29th European Solid-State Circuits Conference, Estoril, Portugal, pp. 683-686, 16-18 Sept. 2003.
[7]H. Ransijn and P.O. Connor, "A PLL-Based 2.5 Gb/s Clock and Data Regenerator IC," IEEE J.Solid-State Circuits, vol. 26, No. 10, pp. 1345-1353, Oct. 1991.
[8]L. DeVito, J. Newton, R. Croughwell, J. Bulzacchelli, and F. Benkley, "A 52 MHz and 55 MHz Clock-Recovery PLL,"
in ISSCC Dig.Tech.Papers, pp. 142-143, Feb. 1991.
[9]A. Pottbacker, U. Langmann, and H.U. Schreiber, "A Si Bipolar Phase and Frequency Detector for Clock Extraction up to 8Gb/s," IEEE J.Solid-State Circuits, vol. 27, pp. 1747-1751, Dec. 1992.
[10]T.S. Chen, Y.B. Luo, and L.R. Huang, "A 10 Gb/s Clock and Data Recovery Circuit with Binary Phase/Frequency Detector using TSMC 0.35um SiGe BiCMOS Process," The 2004 IEEE Asia-Pacific Conference, Tainan, Taiwan, vol. 2, pp. 981-984, 6-9 Dec. 2004.
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