臺灣博碩士論文加值系統

矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製
摘要
在本論文中，我們利用矽鍺/矽異質結構，實際製作出Si1-xGex(x=0、0.3)動態臨界電壓電晶體(Dynamic Threshold Voltage MOSFET, DTMOS)及一般金氧半電晶體(Standard MOS)。並且分別在溫度為77K、150K、300K、350K及400K時，量測其直流特性表現，然後去比較溫度對DTMOS及Standard MOS的影響。除了直流特性分析外，我們也在溫度240K、300K及350K時分別比較元件的低頻雜訊特性。
從我們的量測結果中，可看出SiGe DTMOS的確擁有較Si Standard MOS佳的直流特性、低頻雜訊和熱穩定性，具有在低電壓、低功率及高速應用方面的潛力。
本論文的另一重點為利用嵌入式矽鍺源/汲極結構抑制元件的短通道效應，並且實際使用ICP與LPCVD解決矽鍺源/汲極結構中兩個關鍵製程，嵌入式源/汲極蝕刻與矽鍺選擇性沉積。期待利用此矽鍺源/汲極結構更進一步改良元件性能，以實現未來奈米金氧半電晶體發展之趨勢。

目錄
圖目錄…………………………………………………………………………Ⅰ
表目錄…………………………………………………………………………Ⅴ
序章 論文結構介紹…………………………………………………………Ⅵ

第一章 介紹………………………………………………………………… 1
1-1 前言………………………………………………………………………1
1-2 研究動機…………………………………………………………………2
1-3 研究目的與應用…………………………………………………………3

第二章 元件製程與量測分析……………………………………………… 9
2-1 前言………………………………………………………………………9
2-2 矽鍺/矽異質接面動態臨界電晶體製程步驟………………………… 9
2-3 DTMOS與Standard MOS在常溫下之特性比較…………………………10
2-3-1 Id(Ib)-Vg的特性比較………………………………………………10
2-3-2 臨界電壓的比較 ……………………………………………………11
2-3-3 次臨界擺輻的比較………………………………………………… 12
2-3-4 導通電流的比較…………………………………………………… 13
2-3-5 轉導值的比較……………………………………………………… 14
2-3-6 靜態漏電流的比較………………………………………………… 14
2-3-7 低頻雜訊的比較…………………………………………………… 15
2-3-8 通道長度對DTMOS特性的影響………………………………………16
2-4 DTMOS與Standard MOS在變溫下之特性表現…………………………17
2-4-1 Id(Ib)-Vg對溫度的特性比較………………………………………17
2-4-2 轉導值對溫度的特性比較………………………………………… 18
2-4-3 臨界電壓對溫度的特性比較……………………………………… 19
2-4-4 次臨界擺輻對溫度的特性比較…………………………………… 20
2-4-5 導通電流和截止電流對溫度的特性比較………………………… 20
2-4-6 低頻雜訊對溫度的特性比較……………………………………… 21
2-5 結論…………………………………………………………………… 21

第三章 利用矽鍺源/汲極結構改善DTMOS性能……………………………38
3-1 前言……………………………………………………………… 38
3-2 短通道效應及其改善方法……………………………………… 38
3-3 矽鍺在閘極與源/汲極結構之應用………………………………42
3-4 矽鍺源/汲極之形成方式與模擬分析……………………………44
3-4-1 嵌入式源/汲極結構…………………………………………………44
3-4-2 結構設計…………………………………………………………… 45
3-4-3 摸擬結果與分析…………………………………………………… 45
3-5 結論……………………………………………………………… 47

第四章 嵌入式矽鍺源/汲極結構之關鍵製程開發……………………… 60
4-1 前言……………………………………………………………… 60
4-2 嵌入式源/汲極結構製程步驟…………………………………………60
4-2-1 乾式電漿蝕刻製程設備…………………………………………… 61
4-2-2 間隙壁回蝕刻……………………………………………………… 62
4-2-3 源/汲極等向性蝕刻…………………………………………………64
4-3 複晶矽鍺源/汲極薄膜的沉積…………………………………………64
4-3-1 薄膜沉積製程設備………………………………………… 64
4-3-2 矽鍺選擇性沉積…………………………………………………… 65
4-4 結論……………………………………………………………… 69

第五章 總結與未來展望……………………………………………………79

參考文獻資料……………………………………………………………… 80

參考文獻資料
[1] Fariborz Assaderaghi et al., ‘‘Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra Low Voltage VLSI,’’ IEEE Trans. Electron Device, vol. 44, no. 3, pp. 414-422, 1997.
[2] Fariborz Assaderaghi, et al., ‘‘A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra Low Voltage Operation,’’ IEEE Electron Device Lett., vol 15, no. 12, pp. 510-512, 1994.
[3] Fariborz Assaderaghi, ‘‘DTMOS: Its Derivatives and Variations, and Their Potential Applications,’’ The 12th International Conference on Microelectronics, pp. 9-10, 2000.
[4] Fariborz Assaderaghi et al., ‘‘A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra Low Voltage Operation,’’ IEDM Tech. Dig., pp. 809-812, 1994.
[5] G. W. Taylor, ‘‘Subthreshold conduction in MOSFETs,’’ IEEE Trans. Electron Devices, vol. ED-25, pp. 337, 1978.
[6] R. R. Troutman, ‘‘VLSI limitations from drain-induced barrier lowering,’’ IEEE J. Solid-State Circuits, vol. SC-14, pp. 383, 1979.
[7] V. P. Kesan, et al., ‘‘High performance 0.25um p-MOSFET’s with silicon-germanium channels for 300K and 77K operation,’’ IEDM Tech. Dig., pp. 25, 1991.
[8] S. Verdonckt-Vanderbroek, et al., ‘‘SiGe channel hetero-junction p-MOSFET’s,’’ IEEE Trans. Electron. Devices, vol. 41, no. 90, 1994.
[9] P. W. Li, et al., ‘‘SiGe pMOSFET’s with Gate Oxide Fabricated by Microwave Electron Cyclotron Resonance Plasma Processing,’’ IEEE Electron Device Lett., vol. 15, pp. 402-405, 1994.
[10] Robert J. P. Lander et al., ‘‘High Hole Mobilities in Fully-Strained Si1-xGex Layers(0.3[11] 石靖節，“應變型矽鍺通道金氧半電晶體之研究”，碩士論文，國立中央大學，民國92年。
[12] 郭添賞，“高速低功率P型矽鍺金氧半電晶體之研究”，碩士論文，國立中央大學，民國92年。
[13] 陸新起, ‘‘矽鍺(SiGe)技術與應用, ’’電子月刊,九卷四期, pp.147-159, 2003.
[14] 林鴻志, ‘‘奈米金氧半電晶體元件技術發展驅勢(III),’’ 奈米通訊, 七卷三期, pp. 1-4, 2000.
[15] Akira Asai and Junko Sato-Iwanaga, et al., ‘‘Low-Frequency Noise Characteristics in SiGe Channel Heterostructure Dynamic Threshold pMOSFET(HDTMOS)’’, IEDM, pp.35-38, 2002.
[16] G. W. Taylor, ‘‘Subthreshold conduction in MOSFETs,’’ IEEE Trans. Electron Devices, vol. ED-25, pp. 337, 1978.
[17] Ben G. Streetman, Sanjay Banerjee, ‘‘Solid State Electronic Devices,’’ Chapter 6, 2001.
[18] YAN. R. H., OURMAZD, A., and LEE, K. F., ‘‘From bulk to SOI to bulk,’’ IEEE Trans. ED-39, pp. 1704-1710, 1992.
[19] J. Y. Tsai et al, ‘‘DIBL considerations of extended drain structure for 0.1 um MOSFETs,’’ IEEE Electron Device Lett., EDL-17, pp. 331, 1996.
[20] Y. Taur et al., ‘‘25nm CMOS design considerations,’’ IEDM Tech. Digest, pp. 789, 1998.
[21] T. –J. King et al., ‘‘Electrical properties of heavily doped polycrystalline silicon-germanium films,’’ IEEE tran. Electron Devices, ED-41, pp. 228, 1994.
[22] R. people and J. C. Bean, ‘‘Band alignments of coherently strained GexSi1-x/Si heterostructures on <001> GeySi1-y substrates,’’ Appl. Phys. Lett., vol. 48, pp. 538, 1986.
[23] T. –J. King et al., ‘‘A polycrystalline-Si1-xGex-gate CMOS technology,’’ proc. IEDM, pp. 253, 1990.
[24] V. E. Houtsma et al., ‘‘Stress-induced leakage current in p+ poly MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material,’’ IEEE Electron Device Lett., EDL-20, pp. 314, 1999.
[25] S. A. Campbell et al., ‘‘MOSFET Transistors Fabricated With High Permitivity TiO2 Dielectrics,’’ IEEE Trans. Electron Device, ED-44, pp. 104-109, 1997.
[26] Y. V. Ponomarev et al., ‘‘Gate-workfunction engineering using ploy-(Si,Ge) for high-performance 0.18um CMOS technology,’’ IEDM Tech. Digest, pp. 829, 1997.
[27] C. Isheden et al., ‘‘MOSFETs with Recessed SiGe Source/Drain Junctions Formed by Selective Etching and Growth,’’ Electrochemical and Solid-State Letters, pp. G53-G55, 2004.
[28] R. People, ‘‘Indirect band gap of coherently strained GexSi1-x bulk alloys on <001> silicon substrates,’’ Phys. Rev, vol. B32, pp. 1405, 1985.
[29] T. –J. King et al., ‘‘A low-temperature (≦500oC) silicon-germanium MOS thin-film transistor technology for large-area electronics,’’ Proc. IEDM, pp. 567, 1991.
[30] S. Gannavaram et al., ‘‘Low Temperature (≦800oC) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS,’’ IEDM Tech. Digest, pp. 437, 2000.
[31] 廖偉明，“高效能矽鍺互補型金氧半電晶體之研製”，碩士論文，國立中央大學，民國91年。
[32] 蔡文洲，“矽鍺異質源/汲極結構與pn二極體之研製’’，碩士論文，國立中央大學，民國93年。
[33] J. W. Coburn, and E. Kay, ‘‘Some Chemical Aspects of Fluorocarbon Plasma Etching of Silicon and Its Compounds,’’ Solid State Technol., pp. 117, 1979.
[34] J. W. Coburn, ‘‘Surface-science Aspects of Plasma-assisted Etching,’’ Appl. Phys. A, vol. A59, pp. 451, 1994.
[35] M. M. Millard, and E. Kay, ‘‘Difluocarbene Emission Spectra from Fluorocarbon Plasmas and Its Relationship to Fluorocarbon Polymer Formation,’’ J. Electrochem. Soc., pp. 160, 1982.