臺灣博碩士論文加值系統

論文名稱：奈米CMOS晶片內序列傳輸之傳送器
頁數：87
校所組別：國立中央大學 電機工程研究所 電子組
研究生：王又君 指導教授：鄭國興 教授
周世傑教授
論文提要及內容：

為了高度整合不同功能的模組，系統單晶片技術日趨重要。但傳遞模組間訊息的晶片內部拉線，卻因延遲過長，面積過大以及高複雜度而限制了晶片的效能，尤其以全域性晶片內部拉線更為嚴重。

因此，在此論文中，我們首先根據不同製程下的晶片內部拉線，分析其特性和趨勢，以期在配合電路設計之需要下，能建立較精準的拉線模型。另外，我們也提出應用在晶片內部的序列化傳輸架構，配合所分析的拉線模型，我們設計出一序列化收發器及比較用的一平行化收發器。採用序列化架構的好處是可減少拉線面積及複雜度但不犧牲電路的操作速度。

我們採用台積電130微米 1P8M CMOS 製程，收發器的操作速度分別是5 Gbps 和 4 Gbps，而功率消耗在每條路徑下為0.8 mW 和 2.7 mW，而在同樣的操作速度下，序列化架構拉線面積只有平行化架構拉線面積的一半。

Abstract

Due to the ability of integration many modules with different functions, the system-on-chip is becoming a very interesting solution system method. However, on-chip interconnects that transmit signals between inter-modules limit the performance of chip due to long wire delay, large area, large power consumption and high interconnect complexity. It is especially serious in global on-chip interconnect.
Therefore, in this thesis, we firstly analyze characteristics and trends of the on-chip interconnect with scaling technology nodes. In terms of these analyses, we can establish more accurate interconnect models and it is useful in designing circuits for interconnetcs. Besides, we use serial link technique in on-chip application. With the interconnects models, we design a serial transceiver and a parallel transceiver for comparison. The advantages of serial transceiver are to reduce the interconnect area, reduce interconnect complexity without sacrificing the operational speed of system.
We adopt tsmc 0.13 um 1P8M CMOS process to implement our design, and the operational speed are 5 Gbps and 4 Gbps respectively. The power consumption per channel are 0.8 mW and 2.7 mW respectively, and the interconnect area of serial transceiver is half of parallel one at same operational speed.

Contents

Chapter 1 Introduction ............................................1
1.1 Introduction to System On Chip (SoC) and Network On Chip (NoC)....1
1.2 Motivation and Goals..............................................3
1.2.1 On-chip interconnects................................................3
1.2.2 High-Speed Serial Link Transmitter...................................5
1.3 Thesis Organization...............................................6
Chapter 2 On-Chip Interconnect Analysis............................7
2.1 Background........................................................7
2.1.1 Logic and Wire Delay ................................................9
2.1.2 Insuctance Effects in RLC Interconnect..............................11
2.1.3 Interconenct Model from Berkelry....................................18
2.2 Model of On-Chip Interconnects...................................20
2.2.1 Interconnect Analysis of ITRS Roadmap for Technology Nodes..........20
2.2.2 Channel Characteristics for C foundry and D foundry.................33
2.3 Summary..........................................................43
Chapter 3 On-Chip Transceiver System Overview .....................44
3.1 System Architecture..............................................44
3.1.1 Without Serdes Transceiver (Parallel Version).......................45
3.1.2 With Serdes Transceiver (Serial Version)............................48
3.2 Signaling and Inteference........................................52
3.2.1 Differetial vs. Singled-Ended.......................................52
3.2.2 Reflection..........................................................54
3.2.3 Cross (Couple) Noise................................................55
3.3 Clock Source.....................................................56
3.3.1 VCO.................................................................56
3.3.2 QCG.................................................................57
3.4 Summary..........................................................58
Chapter 4 On-Chip Transmitter Design..............................59
4.1 Architecture.....................................................59
4.2 Circuits Implementation..........................................61
4.2.1 PRBS Encoder........................................................61
4.2.2 Data Synchronizer...................................................63
4.2.3 Parallel-In-Serial-Out (Serializer).................................64
4.2.4 Output Driver.......................................................66
4.3 Pre-emphasis.....................................................67
4.4 Simulation Results...............................................72
4.4.1 Timing Waveform and Eye Diagram.....................................72
4.4.2 Power Analysis......................................................76
4.4.3 Chip Summary and Comparisons........................................77
4.5 Consideration of Cross (Couple) Noise............................79
4.6 Summary..........................................................81
Chapter 5 Experimental Results...................................82
5.1 Layout Consideration.............................................82
5.2 Measurement Consideration........................................84
5.3 Summary..........................................................84
Chapter 6 Conclusions.............................................86
Bibliography..............................................................88

Bibliography



[1] S. Kumar, et. al., “A network on chip architecture and design methodology,” in Proc. of IEEE Computer Society Annual Symposium on VLSI, Apr. 25-26 2002.
[2] G. de Micheli, and L. Benini, “Networks on chip: a new paradigm for systems on chip design,” Conf. design, automation and test in Europe, Mar. 04-08, 2002, p.418.
[3] International Technology Roadmap for Semiconductors (ITRS): Interconnect, Semiconductor Industry Assoc., San Jose, CA, Apr. 25-28 2001, pp. 1-29.
[4] A. B. Kahng, “Overview of the international technology roadmap for semiconductors (ITRS), 2001ed.,” UC San Diego CSE/ECE Depts., June 19, 2002, pp. 1-114.
[5] R. Farjad, C. K. Yang, M. Horowitz, and T. Lee, “A 0.4-μm CMOS 10-Gb/s 4 PAM serial link pre-emphasis transmitter,” VLSI Symposium, June 11-13 1998, pp.198-199.
[6] A. Naeemi, R. Venkatesan, and J. D. Meindl, “Optimal global interconnects for GSI,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 980-987, Apr. 2003.
[7] Y. I. Ismail, E. G. Friedman, and J. L. Neves, “Figures of merit to characterize the importance of on-chip inductance,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 7, no. 4, pp. 442 - 449, Dec. 1999.
[8] http://www-device.eecs.berkeley.edu/~ptm/interconnect.html, the predictive technology model of the Dept. of EECS, University of California, at Berkeley.
[9] M. L. Mui, K. Banerjee, and A. mehrotra, “A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth and power dissipation,” IEEE Trans. Electron Devices, vol. 51, issue. 2, pp. 195-203, Feb. 2004.
[10] TSMC 0.13UM LOGIC 1P8M SALICIDE 1.2V/2.5V FSG IMD manual.
[11] UMC 0.13um Logic and Mixed-Mode 1P8M FSG Process manual.
[12] IEEE Std 1394b-2000: IEEE standard for a high perf.
[13] C. N. Chen, “8Gbps serial link transmitter with adaptive termination resistors and pre-emphasis,” M. S. dissertation, Dept. Elec. Eng., National Central University , Taiwan, June 2004.
[14] M. T. Wong, W.Z. Chen, “A 2.5 Gbps CMOS data serializer,” IEEE Conf. Asia-Pacific, Aug. 6-8 2002, pp. 73-76,.
[15] L. Luo, J. Wilson, S. Mick, J. Xu, P. Franzon, and L. Zhang, “3Gb/s AC-coupled chip-to-chip communication using a low-swing pulse receiver,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 6-10 2005.
[16] A. Fiedler, R. Mactaggart, et al., “A 1.0625Gbps transceiver with 2x -oversampling and transmit signal pre-emphasis,” in Proc. of IEEE International Solid-State Circuits Conference (ISSCC), 1997, pp. 238-239.
[17] F.R. Ramin, et al., “A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter,” IEEE J. Solid-state Circuits, vol.37, pp. 580-585, May 1999.
[18] L. Zhang, J. Wilson, R. Bashirullah, and P. Franzon, “A 2Gb/s/line low power on-chip bus circuit using driver pre-emphasis,” presented at Dept. Elec. Eng., North Carolina State University and University of Florida, 2004.
[19] K. Y. Yun, P. A. Beerel, and J. Arceo, “High-performance two phase micro pipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits,” IEE Proc., Circuits, Devices Syst., vol. 143, no. 5, pp. 282-288, 1996.
[20] K. Lee, S. Lee, and S. Kim, “A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform,” IEEE International Solid-State Circuits Conference (ISSCC), vol. 1, 2004, pp. 152 -518.
[21] J. H. Huang, “Phase-locked loop based multi-phase clock generator”, M. S. dissertation, Dept. Elec. Eng., National Central University , Taiwan, July 2005.