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研究生:曹亞嵐
研究生(外文):YA-LAN TSAO
論文名稱:適用於通訊系統之參數化數位訊號處理器核心
論文名稱(外文):Parameterized DSP Core for Communication System
指導教授:周世傑周世傑引用關係薛木添
指導教授(外文):Shyh-Jye JouMuh-Tian Shiue
學位類別:博士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:161
中文關鍵詞:數位訊號處理參數化架構數位訊號處理器核心
外文關鍵詞:DSP ProcessorDSPParameterized Structure
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本文所撰述為適用於通訊系統之訊號處理器核心完整研究。整體研究包含處理器核心之參數化架構、多重功能之數據處理路徑、內嵌式系統之輸出入介面、低功率設計、可供選擇之特殊功能區塊、模組化訊號處理器核心產生器。
參數化數位訊號處理器核心是設計使核心針對不同應用需求有最佳化之效能。歸功於參數化架構,此數位訊號處理器核心可由使用者自行選定參數以適用所預定之系統。本論文所設定之適用系統為通訊系統。
本論文成功的建立完整設計流程,使數位訊號處理器核心有更彈性的設計特質以及更好的效能表現。
This thesis is a comprehensive work of a parameterized DSP core for embedded system. The overall research includes the parameterized architecture of the DSP core, multi-function data-path, input/output modes for embedded applications, low-power techniques, optional special function blocks and module generator.
Parameterized DSP core is designed for optimal usage of different requirements in system applications. Owing to the parameterized structure, the DSP core can be custom made for dedicated system with parameters setting. The parameterized DSP core is especially suitable for an embedded system. The primary application is digital signal processing system which designed to achieve demodulation/synchronization with better performance and flexibility.
We set up a novel design flow of embedded parameterized DSP core. The design flow includes a newly designed flexible parameterized DSP core structure, a module generator and a methodology to build the DSP core with optimal performance. The features in this DSP core include parameterized data-path, dual MAC unit, sub-word MAC and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low power structure, which includes the gray code addressing mode, pipeline sharing and a novel buffered hardware looping. Users can select the parameters and special function blocks based on the specification of their applications and then a synthesizable DSP core is generated in a proposed module generator with graph user interface.
The proposed DSP core and the synthesizable RTL code have been verified with TSMC 0.35um SPQM, 0.25um 1P5M cell based and FPGA design flow.
Table of Contents
Abstract…………………………………………………….IV
Acknowledgements…………………………………….…V
Table of Contents…………………………………….….VII
List of Figures……………………………………………..X
List of Tables……………………………………………XIV
List of Abbreviations…………………………………….XVI
1. Introduction …………………………………………1
1.1. Motivation and related works …………………………1
1.2. Outline of Thesis ……………………………………5
2. DSP Architecture ……………………………………6
2.1. Overview of DSP architecture ……………………6
2.2. Program Address Generation Unit (PAGU) …………9
2.2.1. Hardware looping ………………………………10
2.2.2. Branch, call and return …………………………13
2.3. Data address generation unit(DAGU) ………………15
2.4. Data path ………………………………………………18
2.4.1. Status register ……………………………………18
2.4.2. Arithmetic logic unit(ALU) ……………………19
2.4.3. MAC unit ……………………………………22
2.4.4. Barrel shifter ……………………………………24
2.5. I/O ……………………………………………………25
2.5.1. Host port interface ………………………………25
2.5.2. Handshaking mode……………………………… 27
2.5.3. DMA mode ……………………………………28
2.5.4. Merge mode ……………………………………30
2.6. Pipeline Sharing ……………………………………30
2.7. Summary ………………………………………………32
3. Parameterized Design Flow …………………………33
3.1. Introduction …………………………………………33
3.2. Parameters …………………………………………33
3.2.1. Data_length, Dmem_size, Pmem_size, HPImem_size, PC_stack_size ……………………………………35
3.2.2. A_width G_width ………………………………36
3.2.3. R_num, …………………………………………36
3.2.4. IO_width …………………………………………36
3.2.5. AR_num …………………………………………36
3.2.6. Loop_num ……………………………………37
3.2.7. Buffer_mem ……………………………………37
3.3. Parameterized design ………………………..…….37
3.3.1. PAGU ……………………………………..….37
3.3.2. DAGU …………………………………………38
3.3.3. Memory architecture …………………………39
3.3.4. Data path …………………………………………40
3.3.5. I/O ………………………………………………41
3.4. Summary ………………………………………………41
4. Special Function Blocks ………………………………43
4.1. Introduction …………………………………………43
4.2. Optional special function blocks ……………………44
4.2.1. Slicer …………………………………………44
4.2.2. Hamming distance calculator ……………………45
4.2.3. Dedicated FIR block …………………………46
4.2.4. Buffered hardware nested looping ………………47
4.2.4.1. Introduction ……………………………………47
4.2.4.2. Implementation ………………………………48
4.2.4.3. Hardware looping ………………………………48
4.2.4.4. Buffered hardware looping ……………………51
4.2.5. Streamed I/O ……………………………………53
4.2.5.1. Introduction ……………………………………53
4.2.5.2. Accumulator I/O ………………………………55
4.2.5.3. Memory connection I/O …………………………55
4.3. Optional multi-function blocks ……………………57
4.3.1. MAC options ……………………………………57
4.3.2. Indirection addressing modes ……………………65
4.4. Design results of optional special function blocks ……65
4.4.1. Hardware overhead of special function blocks 65
4.4.2. Buffered hardware looping ……………………66
4.4.3. Streamed I/O ……………………………………67
5. Low Power Designs ………………………………72
5.1. Introduction …………………………………………72
5.2. Reducing execution cycle …………………………72
5.2.1. Data forwarding ………………………………73
5.2.2. Dual MAC and sub-word MAC…………………..73
5.2.3. Hamming distance calculator ……………………73
5.2.4. Multi-level slicer ………………………………73
5.3. Reducing switching activities …………………………74
5.3.1. Gray code addressing …………………………74
5.3.2. Buffered hardware looping ……………………75
5.3.3. Pipeline sharing ………………………………76
6. Module Generator ……………………………………78
6.1. Introduction …………………………………………78
6.2. Structure consideration ………………………………79
6.3. Parameters consideration …………………………80
6.4. Graph user interface ………………………………80
7. Implementation and Design Results ………………86
7.1. Introduction …………………………………………86
7.2. Chip implementation ………………………………86
7.3. Gray code addressing ………………………………88
7.4. Parameterized design ………………………………88
7.5. Parameterized design evaluation ……………………90
7.5.1. Boundary estimator…………………………… 91
7.5.2. Interpolator ……………………………………93
7.5.3. Timing error detector …………………………96
7.5.4. Loop filter & timing controller ………………98
8. Conclusions …………………………………………102
8.1. Conclusions …………………………………………102
8.2. Future works …………………………………………103
9. References …………………………………………104
Appendix: Instruction Set ………………………………110
List of Publications………………………………………….156
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