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研究生:李典錡
研究生(外文):Dian-Chi Li
論文名稱:覆晶式Ka頻段接收機前端電路與分佈式寬頻放大器之研製
論文名稱(外文):Implementation of the Ka Band Receiver Front-End Circuits with Flip-Chip Package Technology and Distributed Amplifier Design
指導教授:邱煥凱
指導教授(外文):Hwann-Kaeo Chiou
學位類別:碩士
校院名稱:國立中央大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:98
中文關鍵詞:低雜訊放大器接收機前端電路覆晶式
外文關鍵詞:lnareceiver front-end circuitsflip-chip
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論文名稱:覆晶式Ka頻段接收機前端電路與分佈式寬頻放大器之研製
校所組別:國立中央大學 通訊工程研究所 電波組
研究生:李典錡 指導教授:邱煥凱 博士
摘要

隨著影音多媒體服務逐漸普及,因此網路頻寬需求日益增加。毫米波頻段系統提供了較寬的頻帶,滿足了現代通訊高速率與寬頻的需求,因而成為了無線寬頻通訊產品之重要技術,例如區域多點分佈服務系統(LMDS:Local Multipoint Distribution Service)。除了頻譜需求的考量之外,其獨特的優點特別適於高階的無線通訊產品之發展;諸如頻帶寬對載波頻段相對比例較小,因此較容易達到寬頻應用,同時由於其波長大小適中,許多被動元件與天線尺寸不致太小或太大,更加方便實現。接收機前端電路包含低雜訊放大器、寬頻低雜訊放大器以及分佈式寬頻放大器都是其中毫米波頻段接收機系統設計上的重要電路,這領域是一個非常具有發展性的研究主題。
本論文主要研究內容為射頻毫米波頻段前端電路設計,其包含Ka頻段與V頻段。所設計的晶片皆利用WIN 0.15mm pHEMT製程研製,並且將所設計的晶片應用覆晶式封裝技術期望探討其特性,以利未來開發整體接收端系統模組化。
所設計之晶片其量測與模擬結果如下,共平面波導28 GHz低雜訊放大器的增益為28.6 dB,輸入1 dB壓縮點為-15 dBm,雜訊指數為3.5dB;10-30GHz低雜訊放大器的增益為14.5 dB,輸出1 dB壓縮點功率為10 dBm,雜訊指數為6dB;共平面波導分佈式寬頻放大器在頻寬達32GHz內,增益為大於5 dB,輸出1 dB壓縮點功率為大於5 dBm。共平面波導達靈頓分佈式寬頻放大器在頻寬達35GHz內,增益為大於5 dB,輸出1 dB壓縮點功率為大於5 dBm。V頻段低雜訊放大器則增益模擬結果為18 dB,頻寬範圍為10GHz,雜訊指數為4.84 dB。
Title:Implementation of the Ka Band Receiver Front-End Circuits with Flip-Chip Package Technology and Distributed Amplifier Design
School:National Central University Department of Communication Engineering
Student:Dian-Chi Li Advisor:Dr. Hwann-Kaeo Chiou
Abstract
As the wireless multi-media services become more and more popular, therefore broadband wireless access techniques are developed to satisfy these demands. The millimeter wave system takes advantages in the wide frequency range, and matches the trend of high data rate and wide-bandwidth in modern wireless communication system. The millimeter wave system, such as LMDS (Local Multipoint Distribution Service), plays an important role in the wireless-broadband technologies. The receiver circuits include low noise amplifiers, broadband low noise amplifier, and distributed amplifier, which are the key components in LMDS system.
The thesis focuses on the millimeter wave receiver front-end circuit designed, which include the low noise amplifiers in Ka band and V band. The circuits are implemented with WIN 0.15mm pHEMT technology, and then apply the filp-chip package technology to investigate the issues of high frequency interconnects. The integrated millimeter wave front end by flip-chip package will be developed in the next study phase.
The measured and simulated results of the designed circuits are illustrated as followings; for the coplanar waveguide 28GHz LNA, the obtained gain is 28.6 dB, input power at the 1-dB gain compression point is -15 dBm, noise figure is 3.5 dB; for 10-30GHz wideband LNA, the gain is 14.5 dB, output power at the 1-dB gain compression point is 10 dBm, noise figure is 6dB; for the coplanar waveguide distributed amplifier, gain is more than 5 dB within 32GHz bandwidth, output power at the 1-dB gain compression point is more than 5 dBm; for the coplanar waveguide Darlington distributed amplifier, the gain is more than 5 dB in within 35GHz bandwidth, output power at the 1-dB gain impression point is more than 5 dBm. The V-band LNA has 18dB gain and the bandwidth is 10GHz, and noise figure is 4.84 dB.
目錄
第一章 1
緒論 1
1-1 研究動機 1
1-2 研究成果 1
1-3 研究概述 2
第二章 3
毫米波接收機架構及系統參數 3
2-1 接收機架構介紹 3
2-1-1 直接降頻式接收機 3
2-1-2 超外差式接收機 5
2-1-3 結論 6
2-2 接收機系統考量 7
2-2-1 系統靈敏度 7
2-2-2 動態範圍 10
2-2-3 交互調變與三階截取點 11
2-3 LMDS系統規格介紹與應用現況 12
第三章 14
毫米波頻段射頻前端電路設計 14
3-1 簡介 14
3-2 雜訊介紹 15
3-2-1 雜訊來源 15
3-2-2 放大器之雜訊指數 17
3-3 共平面波導之簡介 18
3-3-1 共平面波導之特性探討 19
3-3-2 有限接地平面之共平面波導特性模擬 25
3-4 共平面波導28GHz低雜訊放大器 29
3-4-1 電路架構原理與設計流程 29
3-4-2 電路量測結果 33
3-4-3 結果討論 36
3-5 10-30GHz寬頻低雜訊放大器 37
3-5-1電路架構原理與設計流程 37
3-5-2 電路量測結果 40
3-5-3 結果討論 46
3-6 60GHz低雜訊放大器 47
3-6-1電路架構原理與設計流程 47
3-6-2電路量測與模擬結果 51
第四章 56
分佈式寬頻放大器之設計 56
4-1 分佈式寬頻放大器之介紹 56
4-2 分佈式寬頻放大器之架構 58
4-2-1 傳統分佈式放大器 58
4-2-2 串接式分佈式放大器 59
4-2-3 合成式分佈式放大器 60
4-3 分佈式寬頻放大器之設計原理 61
4-3-1 元件選擇 64
4-3-2 抑制電容效應 65
4-4 增加頻寬之設計方法 66
4-4-1 增加零點設計 66
4-4-2 單位增益頻率倍頻器 68
4-5 共平面波導分佈式寬頻放大器 69
4-5-1電路架構原理與設計流程 69
4-5-2電路量測結果 72
4-5-3 結果討論 76
4-6 共平面波導達靈頓分佈式寬頻放大器 77
4-6-1電路架構原理與設計流程 77
4-6-2 電路量測結果 80
4-6-3 結果討論 84
第五章 85
應用覆晶式封裝技術之電路設計 85
5-1 覆晶封裝技術簡介 85
5-2 覆晶凸塊製作與模型 85
5-3 覆晶式電路設計 88
5-3-1 覆晶式28GHz低雜訊放大器量測結果 89
5-3-2 覆晶式60GHz低雜訊放大器量測結果 92
5-3-3結果討論 94
第六章 95
結論 95
參考文獻 96
參考文獻

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