臺灣博碩士論文加值系統

於現今之半導體朝向高頻、高性能的趨勢下，封裝體之結構可靠度以及電訊特性皆會對封裝系統之效能產生深遠的影響。又，一般而言，封裝可靠度以及高頻訊號傳輸之設計概念大不相同，如於設計封裝體時發生顧此失彼之情形，將會對封裝系統之效能產生嚴重的影響。故吾人從事一微波晶片之封裝設計時，除考慮其與可靠度相關之力學特性外，亦必須將封裝結構對高頻訊號所產生的影響一併考慮，如此才可設計出適合此晶片之封裝結構。綜合以上所述，本研究將分別針對電子封裝結構之力學行為與電訊特性提出其設計與分析之方法，並針對電子封裝之結構可靠度與微波訊號響應之相互影響進行研究及整合分析，以建立一完整的先進電子封裝設計法則。
本研究之測試載具採用具有良好電訊特性與可靠度的覆晶封裝，進行上述各封裝設計法則的分析與探討。本研究針對覆晶封裝結構中，可對其力學行為與電訊特性產生影響之設計參數進行一系列之實驗與有限單元分析。藉由有限單元之模擬分析，吾人可深入瞭解電子封裝結構之力學行為與電磁場分佈特性，再者，配合有限單元參數化分析以及因子設計法（Factorial Design），吾人即可針對電子封裝之效能進行更為深入之研究與設計。另一方面，為探討封裝結構焊錫接點之可靠度（可採用加速熱循環測試實驗）、金屬界層成長之效應（可採用高溫熱儲存實驗）以及其傳送微波訊號之效能（可採用向量網路分析儀量測），本研究設計、製造並量測下列之測試載具：（1）具不同焊錫凸塊結構且未上底膠（Underfill）之覆晶封裝結構、（2）具不同焊錫凸塊材料（錫鉛合金與錫銀無鉛合金）與結構之覆晶封裝、（3）採用銅晶片以及鈦/銅/鎳凸塊下金屬層（UBM）之錫鉛合金凸塊以及錫銀無鉛合金凸塊、（4）可用於微波訊號傳輸之覆晶封裝。研究結果顯示，在經過150oC、1,000小時之高溫熱儲存後，錫鉛合金凸塊之金屬界層成長厚度較錫銀合金凸塊為厚，而錫銀合金凸塊於金屬界層成長後之抗剪強度較錫鉛合金凸塊為佳。另，覆晶封裝結構可靠度之實驗結果顯示，底膠之填充、晶片與基板之墊片尺寸與錫球之體積對焊錫接點的可靠度具有深遠之影響。而在相同的幾何尺寸下，應用錫銀合金凸塊之覆晶封裝具有較應用錫鉛合金凸塊之覆晶封裝為佳的可靠度。於覆晶封裝之微波訊號量測方面，本研究設計之微波訊號傳輸用之覆晶封裝的操作頻率可達3.2GHz。另一方面，為驗證本研究所採用之有限單元分析法，文中亦針對有限單元之模擬分析結果與實驗測試之結果進行比較。其結果指出，無論是結構可靠度之力學行為有限單元分析或是封裝結構之電磁場有限單元分析皆與實驗結果相符，此亦驗證本研究所提出之設計/分析方法的可行性。再者，本研究以上述經驗證過之有限單元分析法針對焊錫接點外型、基板厚度以及底膠填充方式對覆晶封裝可靠度之影響進行因子設計分析，以探討前述設計參數對封裝結構可靠度之敏感度（Sensitivity）以及其交互作用（Interaction）之影響。
為進一步研究電子封裝結構之設計參數對力學行為以及電訊特性之相互影響，本研究針對金屬界層成長以及不同之底膠填充方式對微波訊號傳輸之影響進行分析。一般而言，金屬界層對焊錫接點之力學強度有顯著的影響，然經由微波訊號量測之結果指出，其對微波訊號傳輸的影響並不明顯。另一方面，本研究針對不同底膠填充方式（可分為無底膠、僅於覆晶凸塊陣列之周圍填充底膠與填充底膠於全覆晶凸塊陣列）之覆晶封裝進行微波訊號量測以及可靠度分析。研究結果指出，僅於覆晶凸塊陣列的周圍填充底膠之覆晶封裝具有合適之微波訊號傳輸效能以及優良之可靠度，為一適合用於實際應用之封裝結構。
經由以上分析、設計與實驗之流程，本研究成功的建立起電子封裝之結構可靠度以及微波訊號響應之設計/研究方法。另，本研究亦針對以往經常被分開探討之力學行為以及電訊特性其間之交互影響提出整合設計與討論。以上所述之特點應為本研究之主要貢獻。

Due to the current trend of semiconductors toward higher frequency and better performance, both the structural reliability and the electrical performance of electronic packages can significantly affect the packaging system performance. Therefore, for the electronic packaging design, the mechanical behavior and the electrical performance should be taken into account simultaneously when designing IC chips that operate in the microwave frequency range. Based on the above, this investigation proposes methodologies to analyze and design the electronic packages regarding the mechanical as well as the electrical performance aspects, and to study and integrate the correlation between the reliability and microwave effects in the design methodology development of advanced electronic packaging applications.
A flip chip package, showing good electrical performance and high reliability is selected for this research. To study the aforementioned concerns, the design parameters that can influence the mechanical and electrical performance of a flip chip package are extensively investigated through finite element method (FEM) and several experiments. Through FEM simulation, the mechanical and electromagnetic behavior of the electronic packages could be comprehended and allowing for the parametric as well as factorial analyses of the packaging performance. Moreover, to investigate the solder joint reliability (applying accelerated thermal cycle testing (ATCT)), the IMC growth effect (applying high temperature storage experiment) and the microwave frequency response (applying vector network analyzer (VNA) microwave signal measurement), the following test vehicles: (1) no-underfill flip chip with different solder bump structure, (2) lead-free (96.5Sn/3.5Ag) and eutectic (63Sn/37Pb) solder flip chip with different solder bump structure, (3) lead-free and eutectic solder on Ti/Cu/Ni under bump metallurgy (UBM) layer fabricated upon a copper chip and (4) microwave signal transmission utilizing flip chip are designed, fabricated and tested. The experimental results for the IMC growth effect on the solder bump strength indicate that after isothermal aging treatment at 150oC for more than a 1,000 hours, the Sn/Ag solder reveals a better maintenance of bump strength than the Sn/Pb solder, and the Sn/Pb solder shows a higher IMC growth rate than the Sn/Ag solder. In terms of flip chip package reliability testing, the ATCT experimental results show that the underfilling, die/substrate-side pad size and solder bump volume do indeed play a significant role in the solder joint reliability. In addition, the flip chip utilizing Sn/Ag solder shows a slightly better solder joint reliability than that utilizing the Sn/Pb solder. For VNA microwave signal measurement, the designed microwave flip chip is proven to be feasible under the operation frequency of 3.2 GHz. In addition, to demonstrate the FEM analysis methodologies, the FEM simulation results are compared with the experimental data. The findings indicate that the FEM simulations have good agreement with the experimental results in both mechanical reliability and microwave electrical performance. This confirms the feasibility of the design/analysis methodology developed in this study. Furthermore, based on the validated FEM analysis, the FEM factorial design for the design parameters of the solder joint geometry, substrate thickness and underfill filleting type are employed to study the influence of the design factor sensitivity and the interaction among factors on the flip chip packaging reliability.
In order to investigate the correlation of the mechanical and electrical performance of the electronic package, the IMC layer growth and the underfill fillet type experiment are employed. As is known, the IMC layer formation apparently influences the solder bump mechanical strength, as is contrary to the mechanical impact, the microwave signal testing result shows that there is no significant microwave signal variation that is affected by IMC growth. On the other hand, the microwave signals of test vehicles with a different underfill fillet (without underfill, with peripheral underfill and with full underfill) are measured, and in addition, the solder joint reliabilities of the test vehicles with different underfill fillet are analyzed as well. The findings show that the flip chip with peripheral underfill, showing a qualified microwave signal performance and an excellent mechanical reliability, is recommended for the practical application.
Based on the above, the development of design/research methodologies of the mechanical reliability and the microwave signal performance of electronic packages, and moreover, the integrated discussions between the design considerations of mechanical and electrical aspects of electronic packages which are often investigated independently are the major contributions of this research.

ABSTRACT (CHINESE)
ABSTRACT
ACKNOWLEDGEMENT
TABLE OF CONTENTS
LIST OF TABLES
LIST OF FIGURES
CHAPTER 1 INTRODUCTION
1.1 Motivation of Research
1.2 Literature Survey
1.2.1 Flip Chip Package Design and Solder Joint Reliability Prediction
1.2.2 Lead-Free Solder Reliability and Intermetallic Compounds Effect
1.2.3 Analysis of Electronic Package Radio Frequency Effect
1.3 Research Goal and Methodology
CHAPTER 2 FUNDAMENTAL THEORIES
2.1 Fundamental Theories of Electronic Package Reliability Prediction
2.1.1 Solder Joint Shape Prediction
2.1.2 Hardening Rule
2.1.3 Numerical Method and Convergence Criteria
2.1.4 Solder Joint Reliability Prediction
2.1.5 Statistical Analysis of Reliability Experimental Data
2.1.6 Factorial Design
2.2 Fundamental Theory of Intermetallic Compounds Growth
2.3 Theories for Microwave Electronic Package Design and Measurement
2.3.1 Transmission Line Design Fundamentals
2.3.2 Impedance Matching
2.3.3 Microwave Network Analysis and S parameters
2.3.4 Microwave Signal Measurement
2.3.5 Electromagnetic Field Analysis of Microwave Structure Using Finite Element Method
CHAPTER 3 DESIGN AND FABRICATION OF TEST CHIP AND PACKAGE STRUCTURE
3.1 Flip Chip Package Design
3.2 Lead-Free Solder and No Underfill Flip Chip Package Fabrication
3.3 Microwave Flip Chip Package Design
3.4 Microwave Flip Chip Package Fabrication
CHAPTER 4 FINITE ELEMENT ANALYSIS AND THERMAL CYCLE TESTING FOR ELECTRONIC PACKAGE
4.1 Finite Element Analysis for Lead-Free Solder and No Underfill Flip Chip Package
4.2 Accelerated Thermal Cycle Testing for Lead-Free Solder and No Underfill Flip Chip Package
4.3 Analysis and Comparison between Finite Element Analysis and Thermal Cycle Testing
4.4 Finite Element Factorial Design for Flip Chip Package
CHAPTER 5 INTERMETALLIC COMPOUNDS INVESTIGATION OF EUTECTIC AND LEAD-FREE SOLDER
5.1 Test Vehicle Specifications and Experimental Methodology
5.2 Intermetallic Compounds Experimental Results Analysis and Discussion
CHAPTER 6 ANALYSIS OF MICROWAVE SIGNAL AND INTERACTIVE EFFECT BETWEEN MICROWAVE SIGNAL AND RELIABILITY OF ELECTRONIC PACKAGE
6.1 Analysis of Microwave Signal of Flip Chip Package
6.1.1 Finite Element Analysis of Microwave Signal
6.1.2 Microwave Signal Measurement Using Vector Network Analyzer
6.1.3 Analysis and Comparison between Finite Element Analysis and Experimental Measurement
6.2 Interactive Effect of Design Parameters between Microwave Signal and Reliability
6.2.1 High Temperature Storage Impact on Microwave Signal Performance
6.2.2 Underfilling Type Impact on Microwave Signal and Package Reliability of Flip Chip Package
CHAPTER 7
CONCLUSIONS
REFERENCE
TABLES
FIGURES

1. J. H. Lau, “Flip Chip Technologies,” McGraw-Hill, N.Y., 1995
2. J. H. Lau, C. Chang and Lee, S. -W. R., “Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, Issue: 2, pp. 285-292, June 2001
3. K. N. Chiang, Z. N. Liu and C. T. Peng, ”Parametric reliability analysis of no-underfill flip chip package,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, Issue: 4, pp. 635-640, Dec. 2001
4. J. H. Lau, ”Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 25, Issue: 1, pp. 42-50, Jan. 2002
5. J. H. Lau and S. -W. R. Lee, “Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)”, IEEE Transactions on Components and Packaging Technologies, Vol. 25, Issue: 1, pp. 3-14, March 2002
6. K.M Chen and K.N. Chiang, “Impact of Probing Procedure on Flip Chip Reliability”, Journal of Microelectronics Reliability, Vol. 43, January, 2003, pp. 123-130
7. Y. T. Lin, C. T. Peng and K. N. Chiang, “Parametric Design and Reliability analysis of WIT Wafer Level Packaging,” ASME Transactions on Journal of Electronic Package, Vol. 124, 2002
8. J. H. Lau, “Ball Grid Technology, “McGraw-Hill, Inc., New York, 1995
9. V. Gektin, A. Bar-Cohen and J. Ames, “Coffin-Manson Fatigue Model of Underfilled Flip-Chips,” IEEE Transactions on Components, Packaging, and Manufacturing Technology- Part A, Vol. 20, No. 3, pp. 317 –326, 1997
10. L. F. Coffin, “A Study of the Effects of Cyclic Thermal Stress on a Ductile Metal,” Transactions of ASME, 76, pp. 931-950, 1954
11. S. S. Manson, “Thermal Stress and Low Cycle Fatigue,” McGraw-Hill Book Co., Inc., NY., pp. 125-192, 1966
12. J. H. Lau, “Experimental and Analytical Studies of 28-pin Thin Small Outline Package (TSOP) Solder-Joint Reliability”, ASME Transactions on Journal of Electronic Package, Vol. 114, June, pp. 169-176, 1992
13. H. D. Solomon, “Fatigue of 60/40 Solder”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-9, pp. 91-104, 1986
14. R. Satoh, K. Arakawa, M. Harada and K. Matsui, “ Thermal Fatigue Life of Pb-Sn Alloy Interconnections,” IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 14, No. 1, pp. 224-232, 1991
15. J. P. Clech, “BGA, Flip-Chip and CSP Solder Joint Reliability: of the Importance of Model Validation,” Proc. InterPack, 1999
16. S. Vaynman and S. A. McKeown, “Energy-Based Methodology for the Fatigue Life Prediction of Solder Material,” IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 16, No. 3, pp. 317-322, 1993
17. V. Sarihan, “Energy Based Methodology for Damage and Life Prediction of Solder Joints under Thermal Cycling,“ Electronic Components and Technology Conference, Proceedings, 43rd, IEEE, pp 32-38, 1993
18. J. H. Lau and S. -W. R. Lee, “Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 25, Issue: 1, pp. 3-14, March 2002
19. R. Darveaux and K. Banerji, “Fatigue Analysis of Flip Chip Assemblies Using Thermal Stress Simulations and A Coffin-Manson Relation,” Electronic Components and Technology Conference, 1991. Proceedings, 41st, pp.797-805, 1991
20. Z. Qian and S. Liu, “On the Life Prediction and Accelerated Testing of Solder Joint,” EEP-Vol. 24, Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures, ASME, pp. 1-12, 1998
21. J. H. Lau, S. -W. R. Lee and C. Chang, “Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants,” IEEE Transactions on Components and Packaging Technologies, Vol. 23, Issue: 2, pp. 323 -333, June 2000
22. C. T. Peng, C. M. Liu, J. C. Lin, H. C. Cheng and K. N. Chiang, “Reliability Analysis and Design for the Fine-pitch Flip Chip BGA Packaging”, IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 4, pp. 684-693, Dec. 2004
23. K. A. Brakke, “The Surface Evolver and the Stability of Liquid Surface”, Phil. Trans. R. Soc. Lond. A, Vol. 354, pp. 2143-2157, 1996
24. S. M. Heinrich, M. Schaefer, S. A. Schroeder and P. S. Lee, “Prediction of Solder Joint Geometries in Array-Type Interconnects”, ASME Transaction on Journal of Electronic Packaging, Vol. 118, No. 3, pp. 114-121, Sept., 1996
25. S. M. Lee, S. Shakya, Y. Wang, P. S. Lee and S. A. Schroeder, “Improved Yield and Performance of Ball-Grid Array Packages: Design and Processing Guideline for Uniform and Non-uniform Arrays”, IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B, Vol. 19, No. 2, pp. 310-319, May, 1996
26. K. N. Chiang and W. L. Chen, “Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array”, ASME Transactions on Journal of Electronic Packaging, Vol. 120, No.2, pp. 175-178, June, 1998
27. M. J. Pfeifer, “Solder Bump Size and Shape Modeling and Experimental Validation”, IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B, Vol. 20, No. 4, pp. 452-457, November, 1997
28. K. N. Chiang and C. A. Yuan, “An Overview of Solder Bump Shape Prediction Algorithms with Validations”, IEEE Transactions on Advanced Packaging, Vol. 24, No.2, pp. 158-162, May, 2001
29. A. Schubert, R. Dudek, R. Leutenbauer, R. Doring, J. Kloeser, H. Oppermann, B. Michel, H. Reichl, D. F. Baldwin, Q. Jianmin, S. K. Sitaraman, M. Swaminathan, C. P. Wong and R. Tummala, “Do Chip Size Limits Exist for DCA”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part C: Manufacturing, Vol. 22, No. 4, pp. 255-263, Oct., 1999
30. K. Darbha, J.H. Okura and A. Dasgupta, “Impact of Underfill Filler Particles on Reliability of Flip-Chip Interconnects”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, Vol. 21, No. 2, pp. 275-280, Jun., 1998
31. D. G.. Yang, G.. Q. Zhang, L. J. Ernst, C. Hof, J. F. J. M. Caers, H. J. L. Bressers and J. H. J. Janssen, “Investigation on Flip Chip Solder Joint Fatigue with Cure-Dependent Underfill Properties”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 26 , No.2 , pp. 388-398, Jun. 2003
32. J. H. Lau, C. Chang and S. -W. R. Lee, “Effects of Underfill Material Properties on the Reliability of Solder Bumped Flip Chip on Board with Imperfect Underfill Encapsulants”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part C: Manufacturing, Vol. 23, No.1, pp. 19-27, Jan., 2002
33. B. Vandevelde and E. Beyne, “Improved Thermal Fatigue Reliability for Flip Chip Assemblies Using Redistribution Techniques”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, Vol. 23, No. 2, pp. 239-246, May 2000
34. S. F. Popelar, “A Parametric Study of Flip Chip Reliability Based on Solder Fatigue Modeling”, 1997 IEEE/CMPT International Electronic Manufacturing Technology Symposium, pp299-307, 1997
35. L. L. Mercado and V. Sarihan, “Predictive Design of Flip-Chip PBGA for High Reliability and Low Cost”, 49th Electronic Components and Technology Conference, San Diego, CA, USA, pp. 1111-1115, 1999
36. B. Vandevelde, E. Beyne, G.. Q. Zhang, J. Caers, D. Vandepitte and M. Baelmans, “Parameterized Modeling of Thermomechanical Reliability for CSP Assemblies”, Journal of Electronic Packaging, Transactions of ASME, Vol. 25, pp. 498-505, December, 2003
37. M. Hamada, “Using Statistically Designed Experiments to Improve Reliability and to achieve Robust Reliability”, IEEE Transactions of Reliability, Vol. 44, No. 2, pp. 206-215, June, 1995
38. Z. Johnson, “Implementation of and Extension to Darveaux’s Approach to Finite-Element Simulation of BGA Solder Joint Reliability”, Electronic Components and Technology Conference, pp. 1190-1195, 1999
39. G. Gustafsson, I. Guven, V. Kradinov and E. Madenci, “Finite Element Modeling of BGA Packages for Life Prediction”, Electronic Components and Technology Conference, pp. 1059-1063, 2000
40. L. L. Zhang, S. S. Chee, A. Maheshwari and A. Funcell, “Experimental and Finite Element Analysis of Cavity Down BGA Package Solder Joint Reliability”, Electronic Components and Technology Conference, pp. 391-397, 2000
41. L. L. Zhang, S. S. Chee and A. Maheshwari, “Effect of solder Ball Pad Design on Cavity Down BGA Solder Joint Reliability”, Electronic Components and Technology Conference, pp. 1001-1006, 2002
42. A. Yeo, C. Lee and J. H. L. Pang, “Flip Chip Solder Joint Fatigue Life Model Investigation”, Electronic Components and Technology Conference, pp. 107-114, 2002
43. B. Rosner, J. Liu and Z. Lai, “Flip Chip Bonding Using Isotropically Conductive Adhesives”, Electronic Components and Technology Conference, pp. 578-581, 1996
44. D. F. Baldwin and G. Baynham, “Processing and Reliability of Flip Chip with Lead-Free Solders on Halogen-Free Microvia Substrates”, SEMI Technology Symposium: International Electronics Manufacturing Technology (IEMT) Symposium, pp.310-315, 2002
45. A. Schubert, R. Dudek, R. Doring, H. Walter, E. Auerswald, A. Gollhardt and B. Michel, “Thermo-Mechanical Reliability of Lead-Free Solder Interconnects”, 8th International Symposium on Advanced Packaging Materials, pp. 90-96, 2002
46. M. Li, K.Y. Lee, D. R. Olsen, W. T. Chen, B. T. C. Tan and S. Mhaisalkar, ”Microstructure, Joint Strength and Failure Mechanism of SnPb, and Pb-Free solders in BGA Packages”, IEEE Transactions on Electronics Packaging, Vol.25, No.3, July 2002
47. H. Ezawa, M. Miyata, S. Honma, H. Inoue, T. Tokuoka, J. Yoshioka and M. Tsujimura, “Eutectic Sn-Ag Solder Bump Process for ULSI Flip Chip Technology”, IEEE Transactions on Electronics Package Manufactoring, Vol. 24, No. 4, October 2001
48. J. W. Nah and K. W. Paik, “Investigation of Flip Chip Under Bump Metallization Systems of Cu Pads”, IEEE Transactions on Components and Packaging Technologies, Vol. 25, No. 1, March 2002
49. J. K. Lin, A. D Silva, D. Frear, Y. F. Guo, J. W. Jang, L. Li, D. Mitchell, B. Yeung and C. Zhang, “Characterization of Lead-Free Solders and Under Bump Metallurgies for Flip-Chip Package”, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 25, No. 3, pp. 300-307, July 2002
50. K. L. Lin and K. T. Hsu, “Manufacturing and Materials Properties of Ti/Cu/Electroless Ni/Solder Bump on Si”, IEEE Transactions on Components and Packaging Technologies, Vol. 23, No. 4, pp. 657-660, December 2000
51. Y. Y. Wei and J. G. Duh, “Effect of Thermal Ageing on (Sn-Ag, Sn-Ag-Zn)/PtAg, Cu/Al2O3 Solder Joints”, Journal of Materials Science: Materials in Electronics, 9, pp. 373-381, 1998
52. K. Zeng, V. Vuorinen and J. K. Kivilahti, “Intermetallic Reactions between Lead-Free Sn-Ag-Cu Solder and Ni(P)/Au Surface Finish on PWBs”, Electronic Components and Technology Conference, 2001
53. G. W. Xiao, P. C. H. Chan, A. Teng, J. Cai and M. M. F. Yuen, “Effect of Cu Stud Microstructure and Electroplating Process on Intermetallic Compounds Growth and Reliability of Flip-Chip Solder Bump”, IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 4, pp. 682-690, December 2001
54. B. Salam, N. N. Ekere and D. Rajkumar, “Study of the Interface Microstructure of Sn-Ag-Cu Lead-Free Solders and the effect of solder Volume on Intermetallic Layer Formation”, Electronic Components and Technology Conference, 2001
55. Z. Hou, G. Tian, C. Hatcher, R. W. Johnson, E. K. Yaeger, M. M. Konarsai and L. Crane, “Lead-Free Solder Flip Chip-On-Laminate Assembly and Reliability”, IEEE Transactions on Electronics Packaging Manufacturing, Vol.24, No.4, pp. 282-292, October, 2001
56. C. Zhang, J. K. Lin and L. Li, “Thermal Fatigue Properties of Lead-Free Solders on Cu and NiP Under Bump Metallurgies”, Electronic Components and Technology Conference, 2001
57. M. F. Caggiano, J. Ou, S. Bulumulla and D. Lischner, “RF Electrical Measurements of Fine Pitch BGA Packages”, IEEE Transactions on Component and Packaging Technologies, Vol. 24, No. 2, pp. 233-240, June 2001
58. A. Sutono, N. G. Cafaro, J. Laskar and M. M. Tentzeris, “Experiment Modeling, Repeatability Investigation and Optimization of Microwave Bond Wire Interconnects”, IEEE Transactions on Advanced Packaging, Vol. 24, No. 4, pp. 595-603, November 2001
59. J. Jeong, S. Nam, Y. S. Shin, Y. S. Kim and J. Jeong, “Electrical Characterization of Ball Grid Array Packages from S-Parameter Measurements Below 500MHz”, IEEE Transactions on Advanced Packaging, Vol. 22, No. 3, pp. 343-347, Auguest 1999
60. T. S. Horng, S. M. Wu, C. T. Chiu and C. P. Hung, “Electrical Performance Improvements on RFICs Using Bump Chip Carrier Packages as Compared to Standard Thin Shrink Small Outline Packages”, IEEE Transactions on Advanced Packaging, Vol. 24, No. 4, pp. 548-554, November 2001
61. M. Sung, N. Kim, J. Lee, H. Kim, B. K. Choi, J. M. Kim, J. K. Hong and J. Kim, “Microwave Frequency Crosstalk Model of Redistricbution Line Patterns on Wafer Level Package”, IEEE Transactions on Advanced Packaging, Vol. 25, No. 2, pp. 265-271, May 2002
62. J. Lee, W. Ryu, J. Kim, J. Lee, N. Kim, J. Pak, J. M. Kim and J. Kim, “Microwave Frequency Interconnection Line Model of a Wafer Level Package”, IEEE Transactions on Advanced Packaging, Vol. 25, No. 3, pp. 356-364, August 2002
63. H. Sakai, Y. Ota, K. Inoue, T. Yoshida, K. Takahashi, S. Fujita and M. Sagawa, “A Novel Millimeter-Wave IC on Si Substrate Using Flip-Chip Bonding Technology”, IEEE MTT-S Digest, pp. 1763-1766, 1994
64. T. Hirose, K. Makiyama, K. Ono, T. M. Shimura, S. Aoki, Y. Ohashi, S. Yokokawa and Y. Watanabe, “A Flip-Chip MMIC Design with Coplanar Waveguide Transmission Line in the W-Band”, IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 12, pp. 2276-2282, December 1998
65. H. Kusamitsu, Y. Morishita, K. Maruhashi, M. Ito and K. Ohata, “The Flip-Chip Bump Interconnection for Millimeter-Wave GaAs MMIC”, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 22, No. 1, pp. 23-28, Junnary 1999
66. Z. Feng, W. Zhang, B. Su, K. C. Gupta and Y. C. Lee, “RF and Mechanical Characterization of Flip-Chip Interconnections in CPW Circuits with Underfill”, IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 12, pp. 2269-2275, December 1998
67. K. Onodera, T. Ishii, S. Aoyama, S. S. Sugitani and M. Tokumitsu, “Novel Flip-Chip Bonding Technology for W-Band Interconnections Using Alternate Lead-Free Solder Bumps”, IEEE Microwave and Wireless Components Letters, Vol. 12, No. 10, pp. 372-374, October 2002
68. M. J. Yim, W. Ryu, Y. D. Jeon, J. Lee, S. Ahn, J. Kim and K. W. Paik, “Microwave Model of Anisotropic Conductive Film Flip-Chip Interconnections for High Frequency Applications”, IEEE Transactions on Components and Packaging Technology, Vol. 22, No. 4, 575-581, December 1999
69. R. W. Jackson and R. Ito, “Modeling Millimeter-Wave IC Behavior for Flipped-Chip Mounting Schemes”, IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 10, pp. 1919-1925, October 1997
70. C. L. Wang and R. B. Wu, “A Locally Matching Technique for Broadband Flip-Chip Transition Design”, IEEE MTT-S, pp. 1397-1400, 2002
71. W. Heinrich, A. Jentzsch and G. Baumann, “Millimeter-Wave Characteristic of Flip-Chip Interconnects for Multichip Modules”, IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 12, pp. 2264-2268, December 1998
72. A. Jentzsch. and W. Heinrich, “Optimization of Flip-Chip Interconnects for Millimeter-Wave Frequencies”, IEEE MTT-S, pp. 637-640, 1999
73. A. Jentzsch and W. Heinrich, “Theory and Measurements of Flip-Chip Interconnects for Frequencies up to 100 GHz”, IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 5, pp. 871-878, May 2001
74. Y. K. Yeo, N. Khan and M. K. Iyer, “A Novel Wire Bonded Plastic Chip Scale Package for RF and Microwave Applications”, Electronic Components and Technology Conference, 2001
75. D. Staiculescu, J. Laskar and M. Tentzeris, “Flip Chip Design Rule Development for Multiple Signal and Ground Bump Configurations”, Microwave Conference, 2000 Asia-Pacific, pp. 136-139, December 2000
76. D. Staiculescu, J. Laskar and M. Tentzeris, “Design Rule Development for Microwave Flip-Chip Application”, IEEE Transactions on Microwave Theory and Techniques, Vol. 48, No. 9, pp. 1476-1481, September 2001
77. H. D. Solomon, “Low Cycle Fatigue of Sn96 Solder with Reference to Eutectic Solder and a High Pb solder”, ASME Transactions on Journal of Electronic Packaging, Vol. 113, pp.102-108, June, 1991
78. N. R. Mann, R. E. Schafer and N. D. Singpurwalla, “Methods for Statistical Analysis of Reliability and Life Data,” John Wiley & Sons, Inc., New York, 1974
79. P. C. Chou and H. Miller, “Maximum Likelihood Estimation of a Two-Segment Weibull Distribution for Fatigue Life,” Statistical Analysis of Fatigue Data, ASTM STP 744
80. Y. G. Lee and J. G.. Duh “Interfacial Morphology and Concentration Profile in the Unleaded Solder/Cu Joint Assembly,” Journal of Materials Science: Materials in Electronics, pp. 33-43, 1999.
81. P. T. Vianco, A. C. Kilgo and R. Grant, “Intermetallic Compounds Layer Growth by Solid State Reactions between 52Bi-42Sn Solder and Copper,” ibid. 24, pp. 1493, 1985
82. J. H. Lau, C. P. Wong, N. C. Lee and S. -W. R. Lee, “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”, McGraw-Hill Book Co., Inc., NY., 2003
83. R. Sturdivant, “Reducing the effects of the mounting substrate on the performance of GaAs MMIC flip chips”, Microwave Symposium Digest, IEEE MTT-S International, Vol.3, pp. 1591-1595, 16-20 May, 1995
84. T. C. Edwards and M. B. Steer, “Foundations of Interconnect and Microstrip Design”, 3rd Edition, John Wiley & Sons, Inc., New York, 2000
85. D. M. Pozar, “Microwave Engineering”, John Wiley & Sons, Inc., New York, 1998
86. B. S. Guru and H. R. Hiziroglu, “Electromagnetic Field Theory Fundamentals”, PWS Publishing Company, Boston, 1999
87. C. Y. Chang and S. M. Sze, “ULSI Technology”, McGraw-Hill, 1996
88. S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era, Volume 1”, Lattice Press, Sunset Beach, California, 2000
89. C. T. Peng, C. T. Kuo, K. N. Chiang, T. Ku and K. Cheng, “Experimental Characterization and Mechanical Behavior Analysis of Intermetallic Compounds of Sn-3.5Ag Lead-free Solder Bump with Ti/Cu/Ni UBM Copper Chip”, To be published at Journal of Microelectronics Reliability, 2005
90. J. W. Yoon, S. W. Kim, J.M. Koo, D.G. Kim and S.B. Jung, “Reliability Investigation and Interfacial Reaction of Ball-Grid-Array Packages Using the Lead-Free Sn-Cu Solder”, Journal of Electronic Material, Vol.33, No. 10, pp. 1190-1199, 2004
91. K. C. Chang and K. N. Chiang, “Aging Study on Interfacial Microstructure and Solder Ball Shear Strength of a Wafer-Level CSP with Au/Ni Metallization on a Cu Pad”, Journal of Electronic Materials, V.33, No.11, pp. 1373-1380, November, 2004
92. S. L. Tsao, “Microwave Circuit Theory and Experiment”, Gauli, Taipei, 1999
93. J. C. Lin, “Design, Reliability and Thermal Analysis of Micro-Electronic Devices Packaging with Validations”, PhD Dissertation, Department of Power Mechanical Engineering, National Tsing Hua University, 2003
94. C. M. Liu, “A Study of Effects of Solder Joint Layout, Geometry and Manufacturing Parameters on the Reliability of Micro-Electronic Devices”, PhD Dissertation, Department of Power Mechanical Engineering, National Tsing Hua University, 2004
95. J. H. Lau and Y. H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, 1997
96. D. P. Seraphim, R. C. Lasky and C.Y. Li, “Principles of Electronic Packaging”, McGraw-Hill, 1989