臺灣博碩士論文加值系統

隨著可攜式嵌入式系統(如手機,筆記型電腦，PDA)的普及，大多數的民生消費產品都設計成讓人們可以方便攜帶，因為這些產品是可攜式的，因此待機時間也是消費者的重要考量因素，但是這些產品的用電量卻相當可觀，如何省電就成為重要的研究之ㄧ，另外除了省電的議題之外，即時也是重要的考量，尤其是像手機或無線通訊這類的即時系統也需要快速的反應時間(response time)，如何讓所有在執行的tasks都能夠meet deadlines的情況下還能達到最佳的省電效果是本篇論文探討的重點。
在即時系統中的省電的方式有很多種,常見省電方式可分為兩種：一種是slowdown，另一種是shutdown。Slowdown的方式又分成幾種，像動態電壓調整 (Dynamic voltage scaling)或是動態頻率調整(Dynamic frequency scaling)，這些方式是藉由調降電壓或CPU frequency來達到省電效果,但這種策略只適用於支援多重電壓調整的硬體，而且此種方法會讓周邊的設備消耗更多的電能；而當硬體只支援靜態電壓時,其省電方式為當整個系統處於閒置狀態超過一個臨界時間點,系統會自動shutdown來節省更多電能的消耗，更因為現在的製程技術讓元件愈來愈小，leakage power愈來愈高,使得系統處於閒置狀態時所耗費的電能比以往高，這讓shutdown的機制在整個省電方法中益顯得重要。
本篇論文是在探討在先進製程的系統以及靜態電壓的限制下，如何增加整個系統關閉進入睡眠狀態的時間以及減少關閉跟甦醒之間switch的次數來達到省電的目的，此論文提出一個改良的Procrastination Algorithm –– Enhanced Procrastination Algorithm，以及另一種演算法 –– Pudding Algorithm，並運用此演算法以及EDF的排程策略得到一個即時又省電的排程方法。

In recent years, the products in embedded systems have been growing constantly. Among these development, consumer electronics is the prevalence of electronic equipment intended to be used by people in our daily lives. We can usually find some categories of applications in entertainment, intercommunications, medical appliances, and industrial productivity. For example, mobile phone, PDA, MP3 player, laptop, etc. These systems are ordinarily portable for ideal battery-based products and power management in portable applications is a crucial factor in customer satisfaction and market acceptance. In this scenario, one relevant topic is to increase battery life. In addition, real-time (response time) is an important issue. Some services must be delivered within timing constraints strictly, especially such as mobile phone and wireless communication.
For a real-time system, there are two common ways to reduce the power consumption, that is, the processor shutdown and processor slowdown. The dynamic Voltage Scaling (DVS) approach and the Dynamic Frequency Scaling (DFS) approach make use of the slowdown mode, in which the minimization of the energy consumption performance is achieved through the decreasing of the voltage scaling or the CPU frequency. But this strategy is only suitable for processors supporting multiple-supply-voltage. Thus, it will not only raise execution time of the whole system, but also increase power consumption of peripheral devices. To reduce more electricity consumption, one effective approach is to shutdown the device when the overall system is in an idle period larger than the threshold time. This implies that if the timing requirements are met, the shutdown approach is adequate for reducing overall energy consumption. If we shutdown the system more times, the power saved will be increased.
In this paper, we propose Enhanced Procrastination Algorithm (EPA) scheme. By applying the EPA and the EDF algorithms, more power can be saved.

中文摘要 1
ABSTRACT 3
致謝 5
CONTENTS 6
LIST OF FIGURES 7
CHAPTER 1 INTRODUCTION 8
1.1 Background 8
1.2 Related works 9
1.3 Organization of Thesis 10
CHAPTER 2 PRELIMINARIES 12
2.1 Introduction 12
2.2 Processor Power Model 12
2.3 Leakage Power Control under EDF Scheduling 15
2.4 Procrastination Algorithm 16
CHAPTER 3 POWER SAVING ALGORITHM 19
3.1 Introduction 19
3.2 Problem formulation 19
3.3 Power saving scheduling algorithm 20
CHAPTER 4 EXPERIMENT AND RESULT 27
4.1 Introduction 27
4.2 Experiment environment 27
4.3 Simulation Result 28
4.4 Analysis 30
CHAPTER 5 CONCLUSION 33
5.1 Conclusion 33
5.2 Future work 33
REFERENCE 35

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