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研究生:曾煥鈞
研究生(外文):Huan-Chun Tseng
論文名稱:一個使用平行記憶體的H.264移動補償器
論文名稱(外文):A Motion Compensator with Parallel Memory for H.264 Advanced Video Coding
指導教授:林永隆林永隆引用關係
指導教授(外文):Youn-Long Lin
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:37
中文關鍵詞:先進影像壓縮技術移動補償不同的區塊大小移動向量參考索引參考畫素內插法預測畫素
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我們在這篇論文中提出一個針對先進影像壓縮技術(H.264 Advance Video Coding)的移動補償硬體加速器。我們的設計包含所有先進技術的特性:在動態估計可以使用不同的區塊大小(variable block size)、支援多個參考畫面(multiple reference frame)、支援單一方向的畫面預測(P slice)和兩個方向的畫面預測(B slice)、1/4畫素精確度、不同比重的畫面預估(weight prediction)。為了減少記憶體頻寬(memory bandwidth)和有效的記憶體使用方法(memory usage),我們花了很多時間設計一個新的記憶體儲存架構。我們將此一硬體加速器整合到先進影像壓縮技術的解壓縮器(H.264 decoder)中並做了可程式畫邏輯元件(FPGA)的原型(prototype)。跟先前的設計比較起來,我們的加速器比較小而且較快。
We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports advanced features including variable-block-size motion estimation from multiple reference frames for both P and B slices, quarter-pixel accuracy, and weighted bi-directional prediction. We pay special attention to memory subsystem design for optimizing both memory usage and memory bandwidth. We have integrated the accelerator into an H.264/AVC main profile decoder in FPGA prototype. Compared with previous work, our accelerator is smaller and faster.
ABSTRACT I
CONTENTS II
LIST OF FIGURES IV
LIST OF TABLES V
CHAPTER 1 1
INTRODUCTION 1
CHAPTER 2 5
RELATED WORK 5
2.1 MOTION COMPENSATION ALGORITHM 5
2.1.1 Reference Index Generation 6
2.1.2 Motion Vector Generation 7
2.1.3 Quarter Pixel Accuracy Luminance Interpolation 10
2.1.4 One-eighth Pixel Accurate Chrominance Interpolation 12
2.2 PREVIOUS DESIGNS 12
2.2.1 Increased FIR Filter Utilization 12
2.2.2 Reduce Memory Access 13
CHAPTER 3 14
PROPOSED ARCHITECTURE 14
3.1 MOTION COMPENSATOR OVERVIEW 14
3.2 MOTION COMPENSATION COMPONENTS 15
3.2.1 Motion Vector and Reference Index Generation 15
3.2.2 Interpolation 16
3.2.3 Luminance Interpolation 17
3.2.4 Memory Subsystem 18
3.2.5 Chrominance Interpolation 20
3.2.6 Weight Prediction 23
3.2.7 Modified Interpolation Equation 23
CHAPTER 4 26
EXPERIMENTAL RESULTS 26
CHAPTER 5 29
CONCLUSIONS 29
BIBLIOGRAPHY 30
APPENDIX A1 33
APPENDIX A2 35
[1]Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG (ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6) “Proposed Draft Errata List with Revision-Marked Corrections for H.264/AVC”, 10th Meeting: Waikoloa, Hawaii, 8-11 Dec., 2003
[2]J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, T. Wedi, “Video coding with H.264/AVC: tools, performance, and complexity”, IEEE Circuits and Systems Magazine, Volume : 4, Issue : 1, First Quarter, 2004, Pages : 7 - 28
[3]J. M. Boyce, “Weighted prediction in the H.264/MPEG AVC video coding standard”, Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS’04, Volume : 3, 23-26 May 2004 Pages : 789-792
[4]S. H. Wang, W. H. Peng, Y. He, G. Y. Lin, C. Y. Lin, S. C. Chang, C. N. Wang, Phao Chiang, “A platform-based MPEG-4 advanced video coding (AVC) decoder with block level pipelining”, Proceedings of the 2003 Joint Conference of the Fourth International Conference on Information, Communications and Signal Processing and the Fourth Pacific Rim Conference on Multimedia , Volume: 1 , 15-18 Dec. 2003
Pages:51 - 55
[5]Joint Video Team (JVT) software JM8.3
[6]A. Luthra, G. J. Sullivan, and T. Wiegand, “Introduction to the special issue on the H.264/AVC video coding standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, Issue 7, pp557 – 559, July 2003.
[7]M. Sima, Zhou Y. Zhou, W. Zang, “An efficient architecture for adaptive deblocking filter of H.264/AVC video coding,” IEEE Transactions on Consumer Electronics, vol. 50, Issue 1, pp 292 – 296, February 2004
[8]A. Smoliæ, Y. Vatis, H. Schwarz, T. Wiegand “Long-term Global Motion Compensation for Advanced Video Coding” Proc. 10. Dortmunder Fernsehseminar, ITG/FKTG-Fachtagung, Dortmund, Germany, September 2003
[9]D. Lei, G. Wen, H. M. Zeng, J. Z. Zhou “An efficient VLSI implementation of MC interpolation for MPEG-4,” Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, July 19-21, 2004, Pages:149 - 152
[10]T. A. Lin, T. M. Liu, C. Y. Lee “A Low-Power H.264/AVC Decoder”, Proceedings of the 2004 International Symposium on VLSI Design, Automation and Test, 2005, April 27-29, Page : 278-281
[11]H. Y. Kang, K. A. Jeong, J. Y. Bae, Y. S. Lee, S. H. Lee “MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller” Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 2, 23-26 May 2004 , Page(s):II - 145-8 Vol.2
[12]C. R. Chang “An IP-based Prototype for H.264 decoder”
[13]http://iphome.hhi.de/suehring/tml/ “JVT Reference Software JM8.3”
[14]http://www.novas.com
[15]M. Keating, P. Bricaud “Reuse Methodology Manual for System on a Chip Designs
[16]http://www.transeda.com
[17]S. Z. Wang, T. A. Lin T. M. Liu, C. Y. Lee “A New Motion Compensation Design for H.264/AVC Decoder” Proceedings of the 2005 International Symposium on Circuits and Systems” ISCAS '05, 23-26 May 2005
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