臺灣博碩士論文加值系統

近幾年來，由於低溫多晶矽技術的發展，利用低溫多晶矽所發展的”System-on-glass (SOG)”顯示器相關的技術也快速成長。低溫多晶矽薄膜電晶體似乎可以實現更有附加價值的顯示器。然而對一系統而言，記憶體似乎是一個最基本但也最重要的組成之一，以目前記憶體相關的技術，由於溫度與製程上的考量，矽-二氧化矽-氮化矽-二氧化矽-矽 (SONOS)的結構可能是目前較適合的選擇。
在成長氮化矽的過程中，我們以別於傳統利用低壓化學氣相沉績以氨氣與Silane為反應氣體的方式，我們利用電漿輔助化學氣相沉積法成長過矽氫化非晶矽薄膜，成長的氣體為稀釋於氬氣中的Silane與氮氣，成長溫度為室溫。此外，我們固定Silane的流量，改變氮氣的流量藉以調變過矽氫化非晶矽薄膜中矽的含量，以期觀察不同的矽含量對記憶體效能的影響。
而在基板的選擇上，不同於以往通道導通於矽基板上，我們整個記憶體元件成長於低溫多晶矽上，而此低溫多晶矽上載子的遷移率約5 cm2/V.S, 因此，元件在電流與電壓關係上的表現勢必將受影響，連帶著在效能上亦可能不如以往在以單晶矽基板為通道上的表現。不過以現今低溫多晶矽的技術在遷移率上似乎有還大的改善空間，以期將會有更好的效能。
而堆疊在過矽氫化非晶矽薄膜上下的兩層氧化層，對於整個元件無論是效能上與可靠度上有著重大的影響，但由於製程溫度上的考量，氧化層的品質將會是一個關鍵的問題，而其也將左右整這記憶體元件。在氧化層的選擇上，我們利用電漿輔助化學氣相沉積法，以TEOS與臭氧為其反應氣體，反應的溫度為400 oC。
因此，在整個記憶體元件的製作過程中，除了最後活化源極與汲極，使用快速熱退火以725 oC, 20秒以外，其他的製程溫度皆控制在400 oC以下，雖然活化溫度高達725 oC但由於時間僅20秒，對於玻璃基板而言仍是在一個可承受的範圍內。

Development of the “System-on-glass (SOG)” display with low temperature poly-silicon thin film transistor has rapidly advanced recently due to the advancement of low temperature poly-silicon technology. Low temperature poly-silicon thin film transistor possibly realizes more value-added display. For a system, memory devices seem to be basic and important elements. However, there are various kinds of technology for memory devices. Taking temperature and process into consideration, SONOS-type structure seems the one of the appropriate choice of them.
In the process of depositing silicon nitride, we take different way to deposit it. In conventional process, Silane and NH3 are the precursors to be used to deposit it with low process chemical deposition. And we use Silane and N2 as precursors to deposit si-rich silicon nitride with plasma enhanced chemical vapor deposition at room temperature. Besides, we fix the flow rate of Silane and adjust the rate of N2 flow to change to ratio of silicon in si-rich silicon nitride to observer the influence of silicon content on memory performances.
In the consideration of substrate, we employ low temperature poly silicon as the substrate rather than single crystal silicon substrate. The mobility of the LTPS is 5 cm2/V.S. Therefore, the performance of the current-voltage relation will be affected seriously and the efficiency of the device is not as good as the efficiency of single crystal silicon substrate. Fortunately, there are substantially improvements in the mobility presently to achieve batter performances.
The blocking oxide and tunneling oxide which stacked above and below the silicon nitride have great influences on efficiency and reliability issues. With the restriction of process temperature, the quality of the oxide will be the key issue. Here, we use TEOS and O3 as the precursors with PECVD at 400 oC to deposit blocking and tunneling oxide.
The fabrication temperature is blow 400 oC in the whole memory processes in addition to the temperature for the source and drain activation is 725 oC, 20 second. But this one is still under the tolerance of the glass.

Chinese Abstract ---------------------------------------- Ⅰ
English Abstract ---------------------------------------- Ⅲ
Acknowledgement ------------------------------------------Ⅴ
Contents ------------------------------------------------ Ⅵ
Chap. 1 Introduction ------------------------------------- 1
1.1 Evolvement of Nonvolatile Memory --------------------- 1
1.2 Overview of Method for Poly-Silicon Thin Film -------- 3
1.2.1 As-Deposited Method ------------------------------ 3
1.2.2 Slid Phase Crystallization ----------------------- 4
1.2.3 Pulse Rapidly Thermal Annealing ------------------ 4
1.2.4 Metal Induced Crystallization -------------------- 5
1.2.5 Laser Crystallization ---------------------------- 6
1.3 Motivation ------------------------------------------- 6
Figures -------------------------------------------------- 8
References ---------------------------------------------- 12
Chap. 2 Operation and Mechanism ------------------------- 15
2.1 Carrier Transport Mechanisms in Dielectric ---------- 16
2.2 Memory Transport Mechanisms ------------------------- 16
2.3 Carrier Motion -------------------------------------- 19
2.4 Reliability ----------------------------------------- 20
2.4.1 Over-Erasing ------------------------------------ 20
2.4.2 Disturbs ---------------------------------------- 21
2.4.3 Retention ----------------------------------------- 22
2.4.4 Endurance ----------------------------------------- 22
Figures ------------------------------------------------- 24
References ---------------------------------------------- 28
Chap. 3 Experiment Apparatus, Process and Measurement --- 29
3.1 Plasma Enhanced Chemical Vapor Deposition (PECVD) --- 29
3.2 Process Flow -------------------------------------- 31
3.3 Split Condition ----------------------------------- 32
3.4 Measurement Apparatus ----------------------------- 32
Figures ------------------------------------------------- 34
Chap. 4 Results and Discussion -------------------------- 40
4.1 Device Cross Section & Basic Electric Characteristics 40
4.2 Memory Characteristics ------------------------------ 41
4.3 Reliability ----------------------------------------- 41
4.3.1 Retention --------------------------------------- 41
4.3.2 Cycling ----------------------------------------- 42
4.4 Discussion
Figures ------------------------------------------------- 43
Reference ----------------------------------------------- 58
Chap. 5 Conclusions and Suggestions --------------------- 59

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