快閃記憶體為一非揮發性的記憶體，即儲存在其中的資料不會因為電源的移除而消失，而能維持一段很久的時間。而且因為其特殊的電荷注入機制，可以用簡單的方式達到寫入或是清除資料的效果。現今的3C 產品，手機、數位相機、MP3 player、隨身碟、記憶卡隨處都可以看到快閃記憶體的存在。隨著製程的進步，現在一片快閃記憶體晶片上可達8Gbit 的容量。如此大的容量可想像其測試時間和錯誤診斷的難度也隨著增加。若是有一套有系統的錯誤診斷和縮短測試時間的方法，不僅可以提高良率，也可以縮短測試成本。相關的問題是非常値得我們深入研究探討。
在這篇論文裡面，我們以錯誤型樣(fault pattern)為基礎進行快閃記憶體的錯誤診斷。我們建立一快閃記憶體的記憶體列陣模型，並植入缺陷模型加以模擬，來預測缺陷對快閃記憶體的影響。最後我們得到缺陷的錯誤型樣，並建立了快閃記憶體的缺陷對照庫。實驗結果證實利用這方法我們可以得到最高的診斷解析度。若是再配合電流測試(current testing)的方法，可以再進一步提高快閃記憶體的解析度。並且再進一步根據診斷的結果，縮短診斷方程式還可以節省診斷時間。
第二部份我們針對快閃記憶體的測試流程，提出一有系統的方法來縮短測試快閃記憶體時間。因為快閃記憶體的寫入模式比起隨機讀取記憶體花較長的時間，所以其測試方式不像隨機讀取記憶體一般有大量的重複寫入讀出動作。根據我們的方法，能在不減低其錯誤涵蓋率下，縮短快閃記憶體的測試時間。我們依照此一方法發展了一套自動化縮短測試快閃記憶體時間的工具。利用此自動化縮短測試時間工具在工業界快閃記憶體的測試流程上，有效的縮短了7%的測試時間。

Flash memory is a nonvolatile semiconductor memory which will not lose stored data after removed the power. Flash memory can be programmed or erased electrically on-line, and retains its stored data for a long time, so it is highly suitable for portable storage devices. Flash memory can be found everywhere in 3C products nowadays, for example, mobile phones, DSC, MP3 players, Flash disks, CF cards etc. The capacity of a single Flash memory chip can up to 8Gbit at present. With the increasing capacity, the test time becomes longer and failure analysis becomes more difficult. Thus, systematic methodologies of test time reduction and diagnosis will improve the yield and reduce the test cost for mass production.
In this thesis, we applied the diagnostic methodology that we developed for RAM to Flash memory, modifying as needed. Next, we built an electric model of Flash memory array, then injected defects and performed faulty circuits simulation by using a diagnostic test algorithm. After simulating faulty circuits, we use fault-pattern based diagnostic approach in Flash memory. Finally, we generated the defect dictionary of Flash memory. The resolution of our methodology reached 83.3% in NOR type Flash memory, and 100% in NAND type Flash memory.
Next, we proposed a systematic approach to reduce the test time of Flash memory. The test items of Flash memory are much different to RAM. It is because the write operations (erase and program) of Flash memory take a long time. To minimize the test time, there aren’t many Marchlike patterns applied in Flash memory test in industry. Based on our approach, we can reduce the test time without losing fault coverage. We developed an automatic test time reduction tool according to our methodology, and applied it to an industrial case to further reduce total test time by 7%.

1 Introduction . . . . . . . . . . . . . . . . . . . .1
1.1 Motivation . . . . . . . . . . . . . . . . . . . .1
1.2 Objectives . . . . . . . . . . . . . . . . . . . .2
1.3 Thesis Organization . . . . . . . . . . . . . . . 3
2 Fundamentals of Memory Diagnostics. . . . . . . . . 4
2.1 Functional Fault Models . . . . . . . . . . . . . 5
2.1.1 Conventional RAM Fault Models . . . . . . . . . 5
2.1.2 Flash Memory Specific Fault Models . . . . . . .5
2.2 March Tests for Memories . . . . . . . . . . . . .9
2.3 Memory Fault-type Diagnostics . . . . . . . . . . 11
2.4 MemoryFailureAnalysiswithFailurePatterns . . . . .12
2.5 Fault Pattern Based Memory Diagnostics . . . . . .13
3 Diagnosis of Flash Memory . . . . . . . . . . . . . 15
3.1 Overview of Flash Memory Diagnosis . . . . . . . .16
3.2 Flash Cell Modeling . . . . . . . . . . . . . . . 16
3.2.1 Charge Transfer Mechanism . . . . . . . . . . . 18
3.2.2 NOR Type Flash Cell Modeling . . . . . . . . . .20
3.2.3 NAND Type Flash Cell Modeling . . . . . . . . . 23
3.3 Memory Array Architecture of Flash . . . . . . . .26
3.4 Defect Injection Method . . . . . . . . . . . . . 28
3.5 Diagnostic Test Algorithm . . . . . . . . . . . . 31
3.6 Simulation of Faulty Circuits . . . . . . . . . . 33
3.7 Fault PatternGeneration . . . . . . . . . . . . . 36
3.8 Defect Dictionary Creation . . . . . . . . . . . .36
4 Automatic Test Time Reduction . . . . . . . . . . . 39
4.1 Review of Previous Works . . . . . . . . . . . . .39
4.1.1 Partial and Repeated Test Patterns and Test Items .40
4.1.2 Modified Test Patterns . . . . . . . . . . . . .41
4.2 Overview of Automatic Test Time Reduction . . . . 43
4.3 Proposed Test Time Reduction Approach . . . . . . 47
4.3.1 Phase 1: Correlated Conditions Reduction Phase .47
4.3.2 Phase 2: Correlated Partition Mergence Phase . .49
4.3.3 Phase 3:Most-Efficient Test Item Extraction Phase 51
5 Experimental Results . . . . . . . . . . . . . . . .54
5.1 Experimental Results of Flash Memory Diagnosis . .54
5.1.1 NOR Type Flash Memory . . . . . . . . . . . . . 55
5.1.2 NAND Type Flash Memory . . . . . . . . . . . . .59
5.1.3 Reduced Diagnostic Algorithm. . . . . . . . . . 63
5.1.4 Enhanced Diagnostic Resolution . . . . . . . . .65
5.2 Experimental Results of Flash Memory Test Time Reduction . . .66
5.2.1 Reduced Original Test Program . . . . . . . . . 68
5.2.2 Proposed New Test Algorithm . . . . . . . . . . 69
6 Conclusions and Future work . . . . . . . . . . . .71
6.1 Conclusions . . . . . . . . . . . . . . . . . . . 71
6.2 FutureWork . . . . . . . . . . . . . . . . . . . 72

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