臺灣博碩士論文加值系統

隨著深次微米時代的到來，系統晶片（System-on-Chip---SOC）的設計方式被實現，然而矽智產的再利用衍生出許多測試整合上的困難與挑戰。此外，把測試焦點放在定值故障 (stuck-at fault) 的錯誤涵蓋率 ( fault coverage ) 是不足夠的，因為許多會影響時序的瑕疵會被忽略。因此，在測試整合時，等速測試 (at-speed test) 也需要列入考量。

我們實驗室已擁有的測試存取控制系統（Test Access Control System---TACS）可以解決測試整合的問題。測試存取控制系統包含了相容國際電機工程師協會（IEEE）編號P1500標準的測試介面 ( test wrapper )，一個有彈性的測試存取機制（Test Access mechanism---TAM），以及測試控制器（Test Controller）用來測試定值故障。為了考慮在系統晶片測試上的時序問題，所以我們加強測試存取控制系統的功能使其能夠支援等速測試。也就是說，轉換故障 ( transition fault) 的圖樣可以經由加強的測試存取控制系統傳輸到內嵌在系統晶片的電路並完成等速測試。同時適用於延遲測試 ( delay test ) 的測試介面也被實現在加強的測試存取控制系統。

同時系統晶片的測試整合自動化工具---SOC Test Aid Console，簡稱STEAC，也被加強和修改使得新的功能融合進來。從實驗結果來看，我們的方法簡單而且有效率，可以真正的降低測試整合的成本、縮短測試時間，並且所付出的面積也較小。

The advent of deep-submicron semiconductor technology makes system-on-chip (SOC) possible.
In order to handle the complexity of design methodology, intellectual property (IP) reuse is broadly
adopted. However, the reuse of IP cores leads to challenges in test integration. Additionally, the
focus on stuck-at fault coverage is insufficient for the nanometer age, since many defects affecting
the performance of circuitry are unintentionally ignored. Therefore, at-speed (performance) testing
needs more consideration in test integration of SOC.
We have proposed a Test Access Control System (TACS) targeting the test integration issues
in SOC where IEEE P1500 Test Wrappers, a flexible test access mechanism (TAM), and the associated
test controller are developed for stuck-at-fault testing. In order to consider the timing issues
in SOC testing, we enhance our TACS with the ability of at-speed testing. Our TACS can apply
not only the test patterns for stuck-at faults but also for timing-related defects. For example, the
transition-fault test patterns generated by commercial tools can be translated automatically to the
system level through our SOC Test Aid Console (STEAC) and applied to the embedded cores with
timing requirements by our pin-efficient TACS Controller. Wrapper Boundary Register cells for
delay test are chosen in our TACS architecture. The test circuitry insertion, test pattern translation
and test scheduling are all operated automatically.
We have applied this test platform to a SOC design of crypto processor, and the experimental
results demonstrate our approach to be simple and efficient—low test integration cost, short total
test time, and small area overhead.

Contents
1 Introduction 1
1.1 Previous Works on Embedded Core Testing . . . . . 1
1.2 Previous Works of Delay Testing . . . . . . . . . 3
1.3 Organization of the Thesis .... . . . . . . . . . 5
2 IEEE P1500 Standard 6
2.1 Scalable Hardware Architecture . . . . . . . . . . . . . . . . . . . . 7
2.2 Wrapper Serial Ports . .. . . . . . . . . . . . . 7
2.3 Wrapper Parallel Ports . . .. . . . . . . . . . . 9
2.4 Wrapper Bypass register . . . . . . . . . . . . . 9
2.5 Wrapper Boundary Register . . . . . . . . . . . . 9
2.5.1 WBR Operation Events . . . . . . . . . . . . . 9
2.5.2 WBR Operation Modes . . . .. . . . . . . . . . 10
2.5.3 WBR Cell Types . . . . . . . . . . . . . . . . 11
2.6 WIR Instructions . . . . . . . . . . . . . . . . . . . . 13
3 Overview of Delay Test 16
3.1 Transition Fault Model . . . . . . . . . . . . . 17
3.2 Gate Delay Fault Model . . . . . . . . . . . . . 17
3.3 Line Delay Fault Model . . . . . . . . . . . . . 18
3.4 Path Delay Fault Model . . . . . . . . . . . . . 18
3.5 At-speed Test Methodology . . . . . . . . . . . 19
3.5.1 Skewed-Load Method . . . . . . . . . . . . . . 20
3.5.2 Broad-Side Method . . . . . . . . . . . . . . 20
3.6 Summary . . . . . . . . . . . . . . . . . . . . 21
4 TACS: Test Access Control System 23
4.1 Overview of TACS . . . . . . . . . . . . . . . . 23
4.2 IEEE P1500 Test Wrapper Design . . . . . . . . . 24
4.2.1 Wrapper Instruction Register . . . . . . . . . 25
4.2.2 Wrapper Boundary Register and Wrapper Bypass Register ..28
4.2.3 Wrapper Concatenation of Serial and Parallel Paths . . . . . . . . . . . . . 28
4.3 Test Controller .. . . . . . . . . . . . . . . . 30
4.4 TAM Architecture . . . . . . . . . . . . . . . . 33
4.5 Test Operations . . . . . . . . . . . . . . . . 34
4.5.1 Test Data Application . . . . . . . . . . . . 37
4.6 Test Time Calculation . . . . . . . . . . . . . 42
5 SOC Test Integration Platform 45
5.1 STEAC: SOC Test Aid Console . . . . . . . . . . .45
5.1.1 Input Specifications of STEAC . . . . . . . . 47
5.1.2 Database of STEAC . .. . . . . . . . . . . . . 48
5.2 Experimental Results . . . . . . . . . . . . . . 50
5.2.1 Test Cost Analysis . . . . . . . . . . . . . . 53
6 Conclusions and Future Work 54
6.1 Conclusions . . . . . . .. . . . . . . . . . . . 54
6.2 Future Work . . . . . . .. . . . . . . . . . . . 55

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