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研究生:鄭吳全
研究生(外文):Wu-Chuan Cheng
論文名稱:5.2GHzCMOS非整數型頻率合成器之設計
論文名稱(外文):5.2GHz CMOS Fractional-N Frequency Synthesizer
指導教授:劉萬榮
學位類別:碩士
校院名稱:國立臺灣海洋大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:96
中文關鍵詞:頻率合成器
外文關鍵詞:Frequency Synthesizer
相關次數:
  • 被引用被引用:1
  • 點閱點閱:332
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本論文提出一個工作在5GHz頻帶上的分數頻率合成器。整數型頻率合成器無法兼顧頻率解析度與鎖頻時間,而分數頻率合成器無上述問題,但會有分數突波產生,其分數突波可由雜訊整形技術消除。本分數頻率合成器包含相位頻率偵測器、電荷泵浦、迴路濾波器、電壓控制振盪器、除頻器、和差調變器。除頻器係使用注入鎖定除頻器當前置除頻器以減少功率消耗,可程式除頻器當多模除頻器。迴路濾波器為二階被動低通濾波器。和差調變器為MASH 1-1-1架構。電壓控制振盪器為LC振盪器,其在1MHz頻率偏移處的相位雜訊為-116dBc/Hz,可調頻率範圍為4.91GHz至5.38GHz。我們使用台灣積體電路製造公司0.18微米CMOS製程設計鎖相迴路,本分數頻率合成器解析度為27KHz,鎖定時間為8微秒。
A 5GHz CMOS fractional-N frequency synthesizer is designed in this thesis. Usually, it is very difficult to reach high frequency resolution and short locking time at the same time for traditional integer-N frequency synthesizer. While fractional-N frequency synthesis allows a PLL to have finer frequency resolution than reference frequency. But it suffers from fractional supers. These fractional spurs can be reduced and suppressed with a delta-sigma modulator technology. This synthesizer is composed of a phase/frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, frequency dividers and a delta-sigma modulator. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of -116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18um CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27KHz and the locking time is 8 us.
目錄

圖目錄 III
表目錄 VIII
第一章 緒論 1
1-1 研究動機 1
1-2 論文組織 3
第二章 分數頻率合成器的系統分析 4
2-1 鎖相迴路的原理與系統分析 4
2-2 鎖相迴路的雜訊分析 9
2-3 分數頻率合成器的原理與設計考量 12
第三章 和差調變器原理與設計 18
3-1 簡介 18
3-2 和差調變器原理與線性模型 19
3-3 三階和差調變器設計 22
第四章 鎖相迴路電路設計 37
4-1 相位頻率偵測器 37
4-2 電荷泵浦 46
4-3 迴路濾波器 49
4-4 電壓控振盪器 53
4-4-1 簡介 53
4-4-2 電壓控制振盪器的雜訊分析 53
4-4-3 電壓控制振盪器設計 55
4-5 除頻器電路 60
4-5-1 前置除頻器 60
4-5-2 多模數除頻器 64
第五章 分數頻率合成器系統模擬 68
第六章 結論與未來研究方向 78
6-1 結論 78
6-2 未來研究方向 79
參考文獻 80
[1]Thomas H. Lee, Hirad Samavati, and Hamid R. Rategh, “5-GHz CMOS Wireless LANs,” IEEE Transactions on Microwave Theory and Techniques, vol. 5,no. 1, January 2002.
[2]B. Miller, and B. Conley , “A multiple modulator fractional divider, ”IEEE the 44th Annua Frequency Control Symposium , pp. 559 - 568, May 1990.
[3]Behzad Razavi , Design of Analog CMOS Integrated Circuits,McGraw-Hill, 2001.
[4]F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. On Communications, November 1980.
[5]Venceslav F. Kroupa, “Noise Properties of PLL Systems, ”IEEE Trans. on Communications, vol. 30, no. 10, Oct. 1982.
[6]Ulrich L. Rohde, Microwave and Wireless Synthesizers, New York : John Wiley & Sons, Inc. 1997.
[7]V. F. KROUPA , Phase Lock Loops and Frequency Synthesis,
New York : John Wiley, 2003.
[8]V. Manassewitsch , Frequency Synthesizers , New York : John Wiley & Sons, 1987.
[9]Y . Matsuya , and K. Uchimura, “A 16-bit oversampling A-to-D conversion technology using triple integration noise shaping,” IEEE J. of Solid-State Circuits, vol. 22, pp. 921-929, Dec. 1987.
[10]J . C. Candy, “A use of double-integration in sigma-delta modula-tion,” IEEE Trans. on Communications, vol. 33, pp. 249-258, Mar. 1985.
[11]D. R . Welland , “A stereo 16-bit delta-sigma A/D converter for digital audio,” J. Audio Eng. Soc., vol. 37, no. 6, pp. 476-484, June 1989.
[12]Brian Miller,and Robert J. Conley , “A Multiple Modulator Fractional Divider, ” IEEE Trans. on Instrumentation and Measurement, vol 40, no 3. June 1991.
[13]K. Uchimura, T. Hayashi, T. Kimura and A. Iwata , “Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators, ” IEEE Transactions on Acoustic ,vol 36 , pp. 1899-1905 , Dec. 1988.
[14]K. Uchimura, T. Hayashi, T. Kimura and A. Iwata , “VLSI- A to D and D to A converters with multi-stage noise shaping modulators, ” IEEE International Conference on ICASSP '86., vol 11, pp. 1545 - 1548 , Apr 1986.
[15]M.H. Perrott, T.L. Tewksbury,and C.G. Sodini , “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, ” IEEE Journal of Solid-State Circuits,vol 32 ,pp. 2048 - 2060 ,Dec. 1997.
[16]T.A.D. Riley, M.A. Copeland , and T.A. Kwasniewski ,
“Delta-sigma modulation in fractional-N frequency synthesis, ”IEEE Journal of Solid-State Circuits, vol 28,pp. 553 - 559 ,May 1993.
[17]Terrence P. Kenny, Thomas A. D. Riley, Norman M. Filiol, and Miles A. Copeland , “Design and realization of a digital ΔΣ modulator for fractional-n frequency synthesis, ” IEEE Trans. on Vehicular Techonlogy, vol. 48 , no. 2, Mar. 1999.
[18]Yasuyuki RiIatsuya, and Yukio Akazawa , “Multi-stage noise shaping technology and its application to precision
measurement, ” the 9th IEEE Instrumentation and Measurement Technology Conference '92.,pp.540-544 , May 1992.
[19]Woogeun Rhee, Bang-Sup Song,, and Akbar Ali , “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator, ” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, Oct. 2000.
[20]Miicahit Kozak , Izzet Kale, Assaad Borjak and Taoufik Bourdi, “A pipelined all-digital delta-sigma modulator for fractional-N frequency synthesis, ” the 17th IEEE Instrumentation and Measurement Technology Conference 2000. ,vol 2 , pp.1153-1157 , May 2000.
[21]B. Agrawal and K. Shenoi, “Design methodology for SDM,” IEEE Trans. Commun., vol. 31, pp. 360-370, Mar. 1983.
[22]W. Bennett, “Spectra of quantized signal,” Bell System Technical Journal , pp. 446-472, July 1948.
[23]Lizhong Sun,and Thieny Lepley, “Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis,” IEEE ISCAS '99. ,pp. 152-155 ,June 1999.
[24]Mucahit Kozak and Eby G. Friedman, “Design and simulation of Fractional-N pll frequency synthesizers,” ISCAS '04, vol. 4 , pp. 780-783, May 2004.
[25]H.O Johansson. , “A simple precharged CMOS phase frequency detector,” IEEE Journal of Solid-State Circuits, vol. 33,pp. 295-299 , Feb. 1998.
[26]Won-Hyo Lee; Jun-Dong Cho; Sung-Dae Lee, “A high speed and low power phase-frequency detector and charge-pump,” IEEE Design Automation Conference,pp. 269-272 ,Jan. 1999.
[27]R.C Chang.,and Lung-Chih Kuo, “A new low-voltage charge pump circuit for PLL,” IEEE International Symposium on Circuits and Systems, pp. 701-704 , May 2000.
[28]E.J Hernandez.,and A. Diaz Sanchez , “Positive feedback CMOS charge-pump circuits for PLL applications,” IEEE Circuits and Systems, pp. 836-839 ,Aug. 2001.
[29]W.O. Keese, “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops,” National Semiconductor Application Note, no. 1001, May 1996.
[30]Thomas H. Lee and Ali Hajimiri , “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, vol 33, pp. 179-194 ,Feb. 1998.
[31]A. Hajimiri and T.H. Lee , “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State Circuits, vol 34, pp. 717-724 ,May 1999.
[32]E. Hegazi , H. Sjoland and A.A. Abidi , “A filtering technique to lower LC oscillator phase noise,” IEEE Journal of Solid-State Circuits, vol 36, pp. 1921-1930 ,Dec. 2001.
[33]Zhenbiao Li , O, Kenneth , “A 900-MHz 1.5-V CMOS
voltage-controlled oscillator using switched resonators with a wide tuning range,” IEEE Microwave and Wireless Components Letters, vol 13, pp. 137-139,April 2003.
[34] S. Levantino , C. Samori ,A. Bonfanti ,S.L.J. Gierkink ,A.L. Lacaita ,and V.Boccuzzi , “Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion ,” IEEE Journal of Solid-State Circuits, vol 37, pp. 1003-1011 ,Aug. 2002.
[35]Hamid R. Rategh, and Thomas H. Lee, “Superharmonic
injection-locked frequency dividers ,” IEEE Journal of
Solid-State Circuits, vol. 34, no. 6, June 1999.
[36]Hamid R. Rategh, Hirad Samavati, and Thomas H. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE Journal on Solid-State Circuits, vol. 35, no. 5, MAY 2000.
[37]Hossein Zarei , Omid Shoaei , S. M. Fakhraie, M. M. Zakeri , “A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process ,” IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, pp. 887-890 ,Dec. 2000.
[38]Michael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation ,” IEEE Journal of Solid-State Circutts, vol. 32, no. 12, December 1997.
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