跳到主要內容

臺灣博碩士論文加值系統

(44.201.97.0) 您好!臺灣時間:2024/04/19 13:49
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:李國豪
研究生(外文):Guo-hau Lee
論文名稱:應用於2.4GHzISM頻帶之三角積分調變頻率合成器
指導教授:呂良鴻
指導教授(外文):Liang-hung Lu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:67
中文關鍵詞:三角積分調變頻率合成器
相關次數:
  • 被引用被引用:0
  • 點閱點閱:158
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在無線通訊系統中,為了在有限的頻寬內容納更多的用戶,窄通道間距以及在頻帶間的快速切換是必須滿足的條件。除小數鎖相迴路(fractional-N phase-locked loop)的架構被廣泛的應用來達成這些需求。為了要減輕雜訊及分數突波(fractional spurs)所造成的問題,我們採用了三角積分調變器(delta-sigma modulator)來減小在頻率合成器頻寬內之雜訊。如此可改善分數突波以及雜訊表現。
本論文實現了一個包含單晶壓控震盪器的2.4 GHz ISM頻帶三角積分調變除小數頻率合成器。藉由運用E-TSPC形式的預除器,除法器電路可以同時實現高速除頻及低功率消耗的特點。此除法器並不需要額外消耗大量功率的預放大器(preamplifier)或緩衝級來驅動。整體晶片包含相位頻率偵測器(PFD),電荷幫浦(CP),壓控震盪器(VCO)以及多除數除法器(MMD)。低通濾波器的部份由外接元件所實現。三角積分調變器的輸出由向量產生器(pattern generator)所提供。晶片以台積電0.35-μm 2P4M CMOS 製程所製作,頻率合成器的功率消耗為 27 毫瓦。量測於鎖定時的相位雜訊為 -97 dBc/Hz @ 1MHz 偏移。晶片的面積為894 × 855 μm2。
In a wireless communication system, narrow channel spacing and fast switching time between channels are desirable to accommodate more users due to the limited frequency band. A fractional-N phase-locked-loop (PLL) architecture is a widely used technique to meet the demands. In order to alleviate the problems caused by fractional spurs and noises, the delta-sigma modulator (DSM) technique is adopted to reduce the phase noise within the synthesizer bandwidth. As a result, the fractional spurs and noises performance can be improved.
A 2.4 GHz ISM-band fractional-N frequency synthesizer with a monolithic voltage-controlled oscillator is presented in this thesis. By utilizing the E-TSPC type prescaler, the divider circuit can achieve both high-speed frequency division and low power consumption. No power hunger preamplifier or buffer is needed to drive the divider. The chip is composed of a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO) and a multi-modulus divider (MMD). The required low-pass filter is provided by off-chip components in this design. The DSM output is provided by pattern generator. Fabricated in a TSMC 0.35-μm 2P4M CMOS technology, the power consumption of the synthesizer is 27mW. The measured phase noise performance in lock state is -97 dBc/Hz @ 1MHz offset. The chip area is 894 × 855 μm2.
Contents
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Basic Concepts of PLL 3
2.1 Linear Model of PLL 4
2.2 Basic Building Blocks 7
2.3 PLL Dynamics 16
2.4 Loop Stability 18
2.5 Summary 19
Chapter 3 Fractional-N Synthesizers and Delta-Sigma
Modulator 21
3.1 Phase Noise and Spurs 21
3.2 Fractional-N Synthesizers 24
3.3 Delta-Sigma Modulator 26
3.4 Implementation of a 3rd order MASH Delta-Sigma
Modulator 30
3.5 Summary 32
Chapter 4 Realization of a CMOS Frequency
Synthesizer 33
4.1 Behavioral Simulation 33
4.2 Voltage Controlled Oscillator 34
4.3 Phase Frequency Detector 37
4.4 Charge Pump and Low Pass Filter 39
4.5 Frequency Divider 40
4.6 PLL Implementation 47
4.7 Summary 49
Chapter 5 Experiment Results 51
5.1 Testing Setup 51
5.2 PLL Measurement 53
Chapter 6 Discussions and Conclusions 61
6.1 Discussions of the Measurement Results 61
6.2 Conclusions 62
[1] Emad Hegazi, and Asad A. Abidi, “A 17-mW Transmitter and Frequency Synthesizer for 900-MHz GSM Fully Integrated in 0.35-m CMOS,” IEEE J. Solid-State Circuits,” vol. 38, pp. 782-792, May 2003.
[2] Bram De Muer, and M. S. J. Steyaert, “A CMOS Monolithic SD-Controlled Fractional-N Frequency Synthesizer for DCS-1800,” IEEE J. Solid-State Circuits, vol. 37, pp. 835-844, July 2002.
[3] Michael H. Perrott, “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2059, Dec. 1997.
[4] Michael H. Perrott, “A Modeling Approach for S—D Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002.
[5] S. Cicero, and Zhenhua Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 1039-1045, July 2000.
[6] Lu Jianhua, and Wang Zhigong, “Design Techniques of CMOS SCL circuits for Gb/s Applications,” ASIC, 2001. Proceedings. 4th International Conference, pp. 559 -562, OCT. 2001
[7] B. Miller, and B. Conley, “A Multiple Modulator Fractional-N Divider,” in Proc. 44th Annu. Symp. Frequency Control, May 1990, pp. 559-567.
[8] T. A. D. Riley, “A Simplified Continuous Phase Modulator Technique,” IEEE Trans. Circuits Syst. II, vol. 41, pp.321-328, May 1994.
[9] Taizo Yamawaki, “A 2.7-V GSM RF Transceiver IC, ” IEEE J. Solid-State Circuits, vol. 32, pp. 2089-2096, Dec. 1997.
[10] M. Kozak, I. Kale, and T. Bourdi, ”A pipelined all-digital delta-sigma modulator for fractional-N frequency synthesis,” IMTC 2000. Proceedings of the 17th IEEE, Vol. 2, pp. 1153-1157, May 2000
[11] June-Ming Hsu, “A 0.18um CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter,” IEEE J. Solid-State Circuits, vol. 38, pp. 603-613, April 2003.
[12] Michael H. Perrott, “A 27 mW CMOS fractional-N synthesizer modulator IC,” IEEE 44th ISSCC, pp.366-367, Feb. 1997.”
[13] Sudhakar Pamarti, and Ian Galton, “A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-Mb/s In-Loop Modulation,” IEEE J. Solid-State Circuits, vol. 39, pp. 49-62, Jan. 2004.
[14] B. Neurauter, and R. Vuketich, “GSM 900/DCS 1800 fractional-N modulator with two-point-modulation,” Microwave Symposium Digest, 2002 IEEE MTT-S International , vol. 1, pp. 425-428, June 2002.
[15] Piazza F, and Qiuting Huang, “A 3 V/650 MHz, 5 V/910 MHz CMOS dual modulus prescaler for low power, low input-amplitude applications,” IEEE Proceedings of the Eighth Annual IEEE International, pp. 259-262 Sept. 1995.
[16] Hun-Hsien Chang, and Jiin-Chuan Wu, “A 723-MHz 17.2-mW CMOS programmable counter,” IEEE J. Solid-State Circuits, vol. 33, pp. 1572-1575, Oct. 1998.
[17] Cicero Vaucher and Dieter Kasperkovitz, “A wide-band tuning system for fully integrated satellite receivers” IEEE J. Solid-State Circuits, vol. 33, pp. 987-997, July 1998.
[18] P. Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, pp. 744-748, May 1996.
[19] R. E. Best, “Phase-Locked Loop: Design, Simulation, and Application” McGraw-Hill Professional, forth edition 1999.
[20] B. Razavi, “RF Microelectronics,” Pretice-Hall, Inc., 1998.
[21] T. A. D. Riley, “Delta-sigma Modulation in Fractional-N Synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
[22] S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., “Delta-Sigma Data Converters,” IEEE press, second edition, 1997.
[23] P.M. Aziz, H.V. Sorensen, J. vn der Spiegel, “An overview of sigma-delta converters,” IEEE Signal Processing Magazine, vol. 13, pp: 61-84, Jan. 1996.
[24] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” in Proc. ISCAS’99, 1999, pp. 545-548.
[25] 3GPP Technical Specification TS 25.101 V4.2.0, “UE Radio Transmission and Reception (FDD),” Release 2001.
[26] 3GPP Technical Specification TS 05.05 V8.9.0, “Radio Transmission and Reception,” Release 1999.
[27] W. S. Djen, “SA8025 Fractional Synthesizer for 2GHz Band Application,” Application note, Philips Semiconductors, 1997
[28] Gunter Marzinger, “Fractional-N PLL based Transmitters for Cellular Phone,” Microwave Symposium Workshop Notes, 2003 IEEE MTT-S International.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊