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1 The National Technology Roadmap for Semiconductors, 1997 Edition, SIA Semiconductor Industry Association. 2 Lloyd R. Harriott, “Limits of Lithography”, Proceeding of the IEEE, vol.89, NO.3, March 2001, pp. 366-374 3 Stephen Y. Chou, Peter R. Krauss, and Preston J. Renstorm, “Imprint of sub-25nm vias and trends in polymers ”, Applied Physics Letters, vol. 67, 1995, pp.3114-3116 4 S. Y. Chou, P. R. Krauss, and P. J. Renstrom, “Imprint of sub-25 nm via and trenches in polymers,” Applied Physics Letters, Vol. 67 (21), pp.3114-3116, November 20, 1995. 5 S. Y. Chou, P. R. Krauss, and P. J. Renstrom, “Imprint lithography with 25-nanometer resolution,” Science, Vol. 272, pp. 85-87, April 5, 1996. 6 S. Y. Chou, P. R. Krauss, and P. J. Renstrom, “Nanoimprint lithography,” Journal of Vacuum Society and Technology B, Vol. 14, pp. 4129-4133, 1996. 7 S. Y. Chou, P. R. Krauss, W. Zhang, and L. Guo, L. Zhuang, “Sub-10 nm imprint lithography and applications,” Journal of Vacuum Society and Technology B, Vol. 15, pp. 2897-2904, 1997. 8 L. Guo, P. R. Krauss, and S. Y. Chou, “Nanoscale silicon field effect transistors fabricated using imprint lithography,” Applied Physics Letters, Vol. 71, pp. 1881-1883, September 29, 1997. 9 P. R. Krauss, and S. Y. Chou, “Nano-compact disks with 400 Gbit/in2 storage density fabricated using nanoimprint lithography and read with proximal probe,” Applied Physics Letters, Vol. 71, pp. 3174-3176, November 24, 1997. 10 W. Wu, B. Cui, X. Sun, W. Zhang, L. Zhuang, L. Kong, and S. Y. Chou, “Large area high density quantized magnetic disks fabricated using nanoimprint lithography,” Journal of Vacuum Society and Technology B, Vol. 16, pp. 3825-3829, 1998. 11 X. Sun, L. Zhuang, W. Zhang, and S. Y. Chou, “Multilayer resist methods for nanoimprint lithography on nonflat surfaces,” Journal of Vacuum Society and Technology B, Vol. 16, pp. 3922-3925, 1998. 12 H. Tan, A. Gilbertson, and S. Y. Chou, “Roller nanoimprint lithography,” Journal of Vacuum Society and Technology B, Vol. 16, pp. 3926-3928, 1998. 13 Z. Yu, S. J. Schablitsky, and S. Y. Chou, “Nanoscale GaAs metal–semiconductor–metal photodetectors fabricated using nanoimprint lithography,” Applied Physics Letters, Vol. 74, pp. 2381-2383, April 19, 1999. 14 J. Wang, X. Sun, L. Chen, and S. Y. Chou, “Direct nanoimprint of submicron organic light-emitting structures,” Applied Physics Letters, Vol. 75, pp. 2767-2769, November 1, 1999. 15 B. Cui, W. Wu, L. Kong, X. Sun, and S. Y. Chou, ” Perpendicular quantized magnetic disks with 45 Gbits on a 4 X 4 cm2 area,” Journal of Applied Physics, Vol. 85, pp. 5534-5536, April 15, 1999. 16 P. Ruchhoeft, M. Colburn, B. Choi, H. Nounu, S. Johnson, T. Bailey, S. Damle, M. Stewart, J. Ekerdt, S. V. Sreenivasan, J. C. Wolfe, and C. G. Willson, “Patterning curved surfaces: Template generation by ion beam proximity lithography and relief transfer by step and flash imprint lithography,” Journal of Vacuum Society and Technology B, Vol. 17, pp. 2965-2969, 1999. 17 M. Colburn, S. Johnson, M. Stewart, S. Damle, T. Bailey, B. Choi, M. Wedlake, T. Michaelson, S. V. Sreenivasan, J. G. Ekerdt, and C. G. Willson, “Step and flash imprint lithography: a new approach to high resolution patterning,” Proceedings of SPIE, Vol. 3676, pp. 379-391, 1999. 18 M. Colburn, T. Bailey, B. J. Choi, J. G. Ekerdt, S. V. Sreenivasan, and C. G. Willson, “Development and advantages of step and flash imprint lithography,” Solid State Technology, Vol. 46, pp. 67-76, 2001. 19 T. C. Bailey, S. C. Johnson, D. J. Resnick, S. V. Sreenivasan, J. G. Ekerdt, and C. G. Willson, “Step and flash imprint lithography: an efficient nanoscale printing technology,” Journal of Photopolymer Science and Technology, Vol. 15 (3): 481, 2002. 20 B. J. Choi, S. Johnson, S. V. Sreenivasan, M. Colburn, T. Bailey, and C. G. Willson, “Partially constrained compliant stages for high resolution imprint lithography,” Proceedings of ASME DETC2000, Vol. 7B: 861, 2000. 21 M. Colburn, A. Grot, B. J. Choi, M. Amistoso, T. Bailey, S. V. Sreenivasan,J. G. Ekerdt, and C. G. Willson, “Patterning non-flat substrates with a low pressure, room temperature imprint lithography process,” Journal of Vacuum Society and Technology B, Vol. 19, pp. 2162-2172, 2001. 22 B. J. Choi, S. V. Sreenivasan, S. Johnson, M. Colburn, and C. G. Willson, “Design of orientation stages for step and flash imprint lithography,” Precision Engineering, Vol. 25, pp. 192-199, 2001. 23 B. J. Choi, M. Meissl, M. Colburn, T. Bailey, P. Ruchhoeft, S. V. Sreenivasan, F. Prins, S. Banerjee, J. G. Ekerdt, and C. G. Willson, “Layer-to-layer alignment for step and flash imprint lithography,” Proceedings of SPIE, Vol. 4343, pp. 436-439, 2001. 24 D. J. Resnick, D. P. Mancini, S. V. Sreenivasan, and C. G. Willson, “Release Layers for Contact and Imprint Lithography,” Semiconductor International, pp. 71-80, June 1, 2002. 25 T. C. Bailey, S. C. Johnson, M. D. Dickey, B. J. Smith, A. T. Jamieson, E. K.Kim, N. A. Stacey, D. Mancini, W. J. Dauksher, K. Nordquist, D. J. Resnick, S. V. Sreenivasan, J. G. Ekerdt, and C.G. Willson, “Recent Advances in Step and Flash Imprint Lithography,” Proceedings of 39th Interface Symposium, 2002. 26 S. C. Johnson, T. C. Bailey, M. D. Dickey, B. J. Smith, E. K. Kim, A. T. Jamieson, N. A. Stacey, J. G. Ekerdt, C. G. Willson, D. P. Mancini, W. J. Dauksher, K. J. Nordquist, and D. J. Resnick, “Advances in Step and Flash imprint lithography,” Proceedings of SPIE, Vol. 5037, pp. 197-202, 2003. 27 D. J. Resnick, D. Mancini, W. J. Dauksher, K. Nordquist, T. C. Bailey, S. Johnson, S. V. Sreenivasan, J. G. Ekerdt, and C. G. Willson, ”Improved step and flash imprint lithography templates for nanofabrication,” Microelectronic Engineering, Vol. 69, pp. 412–419, 2003. 28 T. Bailey, B. J. Smith, B. J. Choi, M. Colburn, M. Meissl, S. V. Sreenivasan, J. G. Ekerdt, and C. G. Willson, “Step and flash imprint lithography: defect analysis,” Journal of Vacuum Society and Technology B, Vol. 19, pp. 2806-2810, 2001. 29 S. V. Sreenivasan, C. G. Willson, N. E. Schumaker, and D. J. Resnick, “Cost of ownership analysis for patterning using step and flash imprint lithography,” Proceedings of SPIE, Vol. 4688, pp. 903-909, 2002. 30 B. J. Smith, N. A. Stacey, J. P. Donnelly, D. M. Onsongo, T. C. Bailey, C. J. Mackay, S. V. Sreenivasan, S. K. Banerjee, J. G. Ekerdt, and C. G. Willson, “Employing step and flash imprint lithography for gate level patterning of a MOSFET device,” Proceedings of SPIE, Vol. 5037, pp. 1029-1034, 2003. 31 D. J. Resnick, W. J. Dauksher, D. Mancini, K. J. Nordquist, T. C. Bailey, S. Johnson, N. Stacey, J. G. Ekerdt, C. G. Willson, S. V. Sreenivasan, and N. Schumaker, “Imprint lithography for integrated circuit fabrication,” Journal of Vacuum Society and Technology B, Vol. 21, pp. 2624-2631, 2003. 32 T. I. Kamins, D. A. A. Ohlberg, R. Stanley Williams, W. Zhang, and S. Y. Chou, “Positioning of self-assembled, single-crystal, germanium islands by silicon nanoimprinting,” Applied Physics Letters, Vol. 74, pp. 1773-1775,March 22, 1999. 33 W. Wu, J. Gu, H. Ge, C. Keimel, and S. Y. Chou, “Room-temperature Si single-electron memory fabricated by nanoimprint lithography,” Applied Physics Letters, Vol. 83, pp. 2268-2270, September 15, 2003. 34 Z. Yu, and S. Y. Chou, “Triangular profile imprint molds in nanograting fabrication,” Nano Letters, Vol. 4, No. 2, pp. 341-344, 2004. 35 J. Wang, X. Sun, L. Chen, L. Zhuang, and S. Y. Chou, “Molecular alignment in submicron patterned polymer matrix using nanoimprint lithography,” Applied Physics Letters, Vol. 77, pp. 166-168, July 10, 2000. 36 W. Zhang, and S. Y. Chou, “Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers,” Applied Physics Letters, Vol. 79, pp. 845-847, August 6, 2001. 37 W. Zhang, and S. Y. Chou, “Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels,” Applied Physics Letters, Vol. 83, pp. 1632-1634, August 25, 2003. 38 Mingtao Li, Lei Chen, Wei Zhang, and Stephen Y Chou, “Pattern transfer fidelity of nanoimprint lithography on six-inch wafers,” Nanotechnology, Vol. 14, pp. 33-36, 2003. 39 S. Y. Chou, L. Zhuang, and L. Guo, “Lithographically induced self-construction of polymer microstructures for resistless patterning,” Applied Physics Letters, Vol. 75, pp. 1004-1006, August 16, 1999. 40 X. Lei, L. Wu, P. Deshpande, Z. Yu, W. Wu, H. Ge, and S. Y. Chou, “100 nm period gratings produced by lithographically induced self-construction,” Nanotechnology, Vol. 14, pp. 786-790, 2003. 41 S. Y. Chou, and C. Keimel, J. Gu, “Ultrafast and direct imprint of nanostructures in silicon,” Nature, Vol. 417, pp. 835-837, June 20, 2002. 42 Q. Xia, C. Keimel, H. Ge, Z. Yu, W. Wu, and S. Y. Chou, “Ultrafast patterning of nanostructures in polymers using laser assisted nanoimprint lithography,” Applied Physics Letters, Vol. 83, pp. 4417-4419, November 24, 2003. 43 Christopher Gound, “Advanced Process Control: Basic Functionally Requirements for Lithography, ” IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2001. 44 Perioff, D.S., “A Four-Point Electrical Measurement Technique for Characterizing Mask Superposition Errors on Semiconductor Wafer, ” IEEE Journal of Solid-State Circuits, Vol.SC-13, No.4, pp.436-444, August, 1978. 45 MacMillen. D. and W. D. Ryden, ”Analysis of Image Field Placement Deviations of a 5 Microlithography Reduction Lens,” Proceeding SPIE: Optical Micro-Lithography-Technology, Vol.334, pp.78-89, 1982. 46 C.K. Peski, “Minimizing Patter Registration Error Through Wafer Stepper Matching Techniques,” Solid State Technology, pp.111-115, May ,1982 47 W. Zapka, et al, “Mix-and-Match EBP/Optical Lithography of 1 MbitChips,"Microelectronic Engineering, vol. 13, no. 1-4, pp. 357-360, Mar, 1991. 48 Fink, I., Neal Sullivan and James, S. Leaks, “Overlay Sample Plan Optimization for the Detection of Higher Order Contributions to Misalignment,” SPIE , Vol.2196 / Integrated Circuit Metrology, Inspection, and Process Control, Ⅷ, pp.389-399, 1994 49 Stauch, H., K, Simon, H.V. Scheunemann and H.L. Huber, “Impact of Chunk Flatness on Wafer Distortion and Stepper Overlay Comparison of Experimental and FEM Results, ” Microelectrionic Engineering, Vol.23, pp.197-201, 1994. 50 Warren W. Flank, Gary E. Flores, Alan Walther and Manny Ferreira, “A Retical Correction Technique to Minimize Lens Distortion Effects,” BACUS Symposium, 1994 51 W. Flack, et al, “Application of Pattern Recognition in Mix-and-Match Lithography,"Proceedings of SPIE - The International Society for Optical Engineering, vol. 2440, pp. 913-927, 1995. 52 Yew, et al, “Mix-and-Match Lithography Processes for 0.1 µm MOS Transistor Device Fabrication,” Proceedings of SPIE - The International Society for Optical Engineering, vol. 2723, pp. 180-188, 1996. 53 G. Flores, et al, “The Implementation and Characterization of Advanced Mix-and-Match Lithography,"Ultratech Stepper. 54 Laplanche, et al, “Mix and Match Capability of E-Beam Direct Write for The 65 nm Technology," Proceedings of SPIE - The International Society for Optical Engineering, vol. 5037 I, pp. 572-582, 2003. 55 T. Zayecz, “ Life Beyond Mix-and-Match: Controlling Sub-0.18µm Overlay Errors,"Semiconductor International, 2000. 56 http://www.molecularimprints.com/Technology/alignment.html 57 C. S. Su and Y. S. Ku, “An Ion Source for Low Energy Ion Scattering Spectrometry ”, Vacuum, vol. 40, 2000, pp. 467 58 http://www.asml.com/NASApp/asmldotcom/show.do?ctx=427 59 D L White, O R Wood Ⅱ, “Novel alignment system for imprint lithography ”, Journal of Vacuum Science & Technology B, vol. 18, 2000, pp.3552-3556 60 Nyyssonen, D., “Theory of optical edge detection and imaging of thick layers,” J. Opt. Soc. Am., 72, pp. 1425-1436,1982. 61 Kirk, C. P., and Nyyssonen, D., “Modeling the Optical Microscope Images of Thick Layers for the Purpose of Linewidth Measurement,” SPIE 538, pp. 179-187, 1985. 62 Yuan, C., and Strojwas, A. J., “Modeling the Optical Alignment and Metrology Schemes Used in Integrated Circuit Manufacturing,” SPIE 1264, pp. 203-218, 1990. 63 Seligson, J. L. et al., “Overlay metrology simulations - Analytical andexperimental validations,” Proceedings of SPIE Vol. 5038, pp.61-69 , 2003. 64 Seligson, J. L. et al., “Overlay Metrology Simulations,” Proceedings of SPIE Vol. 4689, pp. 295-303, 2002. 65 GSOLVER V2.0 Manual, Grating Solver Development Company, Allen, Texas, 1995. 66 Hecht, E., Optics, 3rd Edition, Addison Wesley Longman, New York, New York, 1998. 67 Juergens, R.C. (Eds.), CODE V Reference Manual, Optical Research Associates, Inc., Pasadena, CA, 1998. 68潘政晟,自校準繞射式雷射光學尺之設計與實驗,國立台灣大學應用力 學研究所碩士論文,2001 69 http://211.74.138.227/mtt/index.php 70林鼎晸,用於奈米雷射直寫儀之浪型次波長結構之模擬與研製,國立台 灣大學應用力學研究所碩士論文,2003 71 T. K. Gaylord, “Analysis and Applications of optical diffraction by gratings,” Proceedings of the IEEE 73, pp894-937, 1985 72 C. L. Liu, and J. W. S. Liu, Linear Systems Analysis. New York: McGraw-Hill, 1975 73 P. St. J. Russel, “Power conservation and field structures in uniform dielectric gratings,” J. Opt. Soc. Amer. A, pp293-299, 1984. 74 S. Astilean, P. Lalanne, and M. Palamaru, ”Light transmission through metallic channels much smaller than the wavelength” Opt. Commun 175, pp265-273, 2000 75 K. S. Yee, “ Numerical solution of initial boundary value problems involving Maxwell’s equation in isotropic media,"IEEE Trans. Antenna and Propagat., vol.14, No.3, pp300-307, May 1966. 76 A. Taflove, Computational Electrodynamics The Finite Difference Time-Domain Method,1995. 77 Z. Bi, K. Wu, C. Wu, and J. Litva,“A dispersive boundary condition for microstrip component analysis using the FD-TD method,"IEEE Trans. Antenna. and Propagat., vol. MTT-40, no. 4, pp.774-777, Apr. 1992. 78 O. M. Ramahi, “Complementary operators: A method to annihilate artificial reflections arising from the truncation of computational domain in the solution of partial differential equations,” IEEE Trans. Antenna. and Propagat., vol.43, pp.697-704, Jul. 1995. 79 J. P. Benerger, “A perfectly matched layer for the absorption of electromagnetic waves,” J. Computat. .Phys., vol. 114, pp185-200, 1994. 80 Z. S Sacks, D. M. Kingsland, R. Lee, and J. F. Lee, “A perfectly matched anisotropic absorber for use as absorbing boundary condition,” IEEE Trans. Antenna. and Propagat., vol.43, pp.1460-1463, Jul. 1995. 81 S. D. Gedney, “An Anisotropic Perfectly Matched Layer-Absorbing Medium for the Truncation of FDTD Lattices "IEEE Trans. AP., vol. 44, No. 12, pp. 1630-1639, Dec. 1996. 82 http://www.olympusmicro.com/primer/anatomy/anatomyjava.html 83陳朝光等 編著, 自動控制, 高立圖書有限公司, 1998 84張道弘 編譯, PID 控制理論與實務, 全華科技圖書, 1995
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