跳到主要內容

臺灣博碩士論文加值系統

(44.211.34.178) 您好!臺灣時間:2024/11/03 07:45
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:陳俊揚
研究生(外文):Chun-Yang Chen
論文名稱:多工環境下之快取記憶體漏電流管理
論文名稱(外文):Cache Leakage Management for Multi-Programming Workloads
指導教授:楊佳玲楊佳玲引用關係
指導教授(外文):Chia-Lin Yang
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:37
中文關鍵詞:快取記憶體漏電流多工環境
外文關鍵詞:CacheLeakageMultiprogrmming
相關次數:
  • 被引用被引用:0
  • 點閱點閱:161
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
由於手持設備的普及,在嵌入式系統上,能量消耗成為一個主要的議題。除了動態能量(dynamic energy)之外,靜態能量(static energy)也就是系統漏電近年來也越來越受到重視。有預估報告指出,當製程技術進步到.07時,系統漏電將會佔據全部能源的百分之七十,所以近年來,就有兩種的電路被設計來降低快取記憶體裡的漏電流,也就是State-destructive 和State-preserving,這些電路提供了記憶體低漏電模式,而當有了電路的供給後,也就有一些控制的方法被提出來控制何時需把記憶體放入低漏電模式。過去的快取記憶體漏電流管理研究都專注在單一一個應用程式的特性,不過在實際的系統上,快取記憶體是被多數個程序所共享,因此在這篇論文,我就會利用程序的資訊去管理快取記憶體漏電流。我會根據每一個程序的工作量去分配給其適合的快取記憶體大小,然後分別給執行及暫停的程序不一樣的漏電流管理方法,用這樣的方法,可以省掉第一階層快取記憶體百分之八十四的漏電流,而且不會造成任何的效能損失。
Power consumption is becoming a critical design issue of embedded systems due to the popularity of portable device such as cellular phones and personal digital assistants. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Leakage is projected to account for 70% of the cache power budget in 70nm technology. In recent year, two kinds of circuit technique are presented for reducing leakage
consumption in cache cells: state-destructive and state-preserving. Most leakage energy can be reduced by using effective control to switch leakage mode.
Previous works on cache leakage management are all based on single-application behavior. In real workloads, caches are actually shared by multiple processes. In this paper, I utilize the task-level information to manage cache leakage power. I partition the caches among tasks according to their working set size. I then apply different leakage management policies to the cache regions allocated to active and suspended tasks, respectively. My proposed policies effectively reduce L1 cache leakage energy by 84% on the average for the multi-programming workloads with only negligible degradations in performances.
Abstract i
1 Introduction 1
2 Background on cache leakage management 4
2.1 Source of leakage power consumption . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Circuit techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 State-destructive circuit . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 State-preserving circuit techniques . . . . . . . . . . . . . . . . . . . 8
2.3 Leakage Control Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 Dynamic resizable cache . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 Simple policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.3 No-access policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Task-Aware cache leakage management 13
3.1 Architectural support for cache partition . . . . . . . . . . . . . . . . . . . . 13
3.2 Cache leakage management policy . . . . . . . . . . . . . . . . . . . . . . . . 16
ii
iii
3.2.1 Active-Task Leakage Management Policy . . . . . . . . . . . . . . . . 16
3.2.2 Idle-Task Leakage Management Policy . . . . . . . . . . . . . . . . . 18
4 Experimental Results 19
4.1 Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Active-Task Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Idle-Task Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Effects of Task-Aware Cache Leakage Management . . . . . . . . . . . . . . 27
5 Related Work 30
6 Conclusions 34
[1] N. Majikian and T. S. Abdelrahman, “Drowsy instruction caches:leakage power reduction using dynamic voltage scaling and cache sub-bank prediction,” in Proc. 35th Ann.
Int’l Symp. Microarchitecture (MICRO-35), IEEE CS Press, 2002, pp. pp.219–230.
[2] S. Kaxiras, Z. Hu, and M. Martonosi, “Cache decay: Exploiting generational behavior to reduce cache leakage power,” in Proceedings of the 28th Annual International
Symposium on Computer Architecture, 2001.
[3] K. Flautner, N.S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy caches: Simple techniques for reducing leakage power,” in International Symposium on Computer
Architecture, 2002.
[4] S.H. Yang, M.D. Powell, B. Falsafi, K. Roy, and T.N.Vijaykumar, “Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache memories,” in In Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000.
[5] D. Parikh, Y. Zhang, K. Sankaranarayanan, K. Skadron, and M. Stan, “Comparison of state-preserving vs. non-state-preserving leakage control in caches,” in In Proceedings of the Second Annual Workshop on Duplicating, Deconstructing, and Debunking in conjunction with ISCA-30, 2003.
[6] D. Brooks, V. Tiwari, and M. Martonosi., “Wattch: A framework for architectural-level power analysis and optimizations,” in In Proceedings of the 27th International
Symposium on Computer Architecture (ISCA), 2000.
[7] C. Lee, M. Potkonjak, and W. H. Mangione-Smith, “Media-bench: A tool for evaluating and synthesizing multimedia and communications systems,” in In Proceedings of the
30th Annual International Symposium on MicroArchitecure, 1997.
[8] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown,“Mibench: A free, commercially representative embedded benchmark suite,” in IEEE 4th Annual Workshop on Workload Characterization, 2001.
[9] J.C.Mogul and A.Borg, “The effect of context switches on cache performance,” in Proceedings of the 4th international conference on architectural support for programming languages and operating systems, 1991.
[10] S. Velusamy, K. Sankaranarayanan, D. Parikh, T. Abdelzaher, and K. Skadron, “Adaptive cache decay using formal feedback control,” in Proc. of the 2002 Workshop on
Memory Performance Issues, May 2002.
[11] J. S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir, “Exploiting program hotspots and code sequentiality for instruction cache leakage manage-
ment,” in Proc. of the International Symposium on Low Power Electronics and Design(ISLPED’03), August 2003.
[12] B. Allu and W. Zhang., “Static next sub-bank prediction for drowsy instruction cache,”in International conference on cumpilers, architecture, and synthesis for embedded systems(CASES’04), September 2004.
[13] L. Li, I. Kadayif, Y-F Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Siva subramaniam, “Leakage energy management in cache hierarchies,” in Proceeding of
Eleventh International Conference on Parallel Architectures and Compilation Techniques, 2002.
[14] W. Zhang, M. Karakoy, M. Kandemir, and G. Chen, “A compiler approach for reducing data cache energy,” in Proceedings of the 17th annual international conference on
Supercomputing, 2003.
[15] W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin,“Compiler-directed instruction cache leakage optimization,” in 35th Annual International Symposium on Microarchitecture (MICRO-35), November 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top