臺灣博碩士論文加值系統

在深次微米的製程技術環境中，溫度成為設計處理器的重要考量因素。處理器的溫度往往受到下面兩個因子的影響：每個處理器元件的耗電功率及處理器內元件的幾何位置擺設。因此，在溫度感知的微計算機結構設計中，吾人需妥善考慮處理器內元件的幾何位置擺設對溫度所造成的影響。在這篇論文當中，我們從微計算機結構層的觀點，提出一個溫度感知的「處理器元件幾何位置擺設方法」架構。透過這個架構，計算機結構設計者能夠結合實體設計暨計算機結構領域，找出一個滿足溫度限制且最佳化效能的處理器元件幾何位置擺設。

Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is a®ected by both the power consumption of processor components and the chip layout. Therefore, for thermal-aware design it is crucial to consider the thermal e®ects of di®erent °oorplans during micro-architectural design space exploration. In this thesis, I propose a thermal-aware architectural °oorplanning framework. With the aid of this framework, an architect can explore both physical and architectural design spaces simultaneously to ‾nd an architecture and the corresponding chip layout that optimizes performance under a thermal limitation.

Abstract i
1 Introduction 1
2 Related Works 4
2.1 Thermal Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal-Driven Floorplanning/Placement . . . . . . . . . . . . . . . . . . . 5
2.3 Dynamic Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Micro-Architectural Floorplanning with Joint Exploration of Architectural
and Physical Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Overview of Thermal-Aware Micro-Architectural Floorplanning Frame-
work 9
4 Design of the Micro-Architectural Floorplanner 12
4.1 Review of the B¤-tree Representation and Simulated Annealing . . . . . . . . 12
4.2 Floorplanning Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Empty Space Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Experimental Results 24
6 Conclusion 30

[1] ITRS, The international technology roadmap for semiconductors," 2003.
[2] K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, Temperature-aware microarchitecture: Extended discussion and results," Techincal Report, CS-2003-08, University of Virgina, Apr. 2003.
[3] G. Chen and S. Sapatnekar, Partition-driven standard cell thermal placement," In Proceedings of the 2003 International Symposium on Physical Design (ISPD), pp. 75{80, Apr. 2003.
[4] S. Gunther, F. Binns, D. M. Canmean, and J. C. Hall, Managing the impact of
increasing microprocessor power consumption," Intel Technology Journal, Q1 2001.
[5] T. Pering, T. Burd, and R. Brodersen, The simulation and evaluation of dynamic
voltage scaling algorithms," In Proceedings of the 1998 International Symposium on
Low Power Electronics and Design (ISLPED), pp. 76{81, August 1998.
[6] D. Brooks and M. Martonosi, Dynamic thermal management for high-performance microprocessors," In Proceedings of the 7th International Symposium on High Performance Computer Architecture (HPCA), pp. 171{182, Jan. 2001.
[7] W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy, Compact thermal modeling for temperature-aware design," In Proceedings of the 36th Conference on Design Automation (DAC), June 2004.
[8] V. Agarwal, M. Hrishikesh, S. Keckler, and D. Burger, Clock rate versus ipc: The
end of the road for conventional microarchitectures," In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA), pp. 248{259, 2000.
[9] E. Sprangle and D. Carmean, Increasing processor performance by implementing
deeper pipelines," In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA), pp. 25{34, 2002.
[10] G. Reinman, T. Austin, and B. Calder, A scalable front-end architecture for fast
instruction delivery," In Proceedings of the 26th Annual International Symposium on
Computer Architecture (ISCA), pp. 234{245, May 1999.
[11] J. Cong, A. Jagannathan, G. Reinman, and M. Romesis, Microarchitecture evaluation with physical planning," In Proceedings of the 36th Conference on Design Automation (DAC), pp. 32{35, June 2003.
[12] M. Ekpanyapong, J. R. Minz, T. Watewai, H.-H. S. Lee, and S. K. Lim, Pro‾le-guided microarchitectural °oorplanning for deep submicron processor design," In Proceedings of the 36th Conference on Design Automation (DAC), pp. 634{639, June 2004.
[13] T. Wang and C. Chen, Thermal-ADI: A linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit(ADI) method," In Proceedings of the 2001 International Symposium on Physical Design (ISPD), pp. 238{243, Apr. 2001.
[14] T. Wang and C. Chen, 3-D Thermal-ADI: A linear-time chip level transient thermal simulator," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, Dec. 2002.
[15] H. Eisenmann and F. M. Johannes, Generic global placement and °oorplanning," In Proceedings of the 35th Conference on Design Automation (DAC), pp. 269{274, June 1998.
[16] C. Chu and D. F. Wong, A matrix synthesis approach to thermal placement," IEEE Transactions on Computer-Aided Design, vol. 17, pp. 1166{1174, Nov. 1998.
[17] C.-H. Tsai and S.-M. Kang, Cell-level placement for improving substrate thermal distribution," IEEE Transactions on Computer-Aided Design, vol. 19, pp. 253{266, Feb. 2000.
[18] D. Grunwald, A. Klauser, S. Manne, and A. Pleszkun, Con‾dence estimation for speculation control," In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), pp. 122{131, June 1998.
[19] C.-H. Lim, W. Daasch, and G. Cai, A thermal-aware superscalar microprocessor," In Proceedings of the International Symposium on Quality Electronic Design (ISQED), pp. 517{522, Mar. 2002.
[20] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, B*-trees: A new representation for non-slicing °oorplans," In Proceedings of the 37th Conference on Design Automation (DAC), pp. 458{463, June 2000.
[21] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671{680, May 1983.
[22] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, Rectangle-packing based module placement," In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 472{479, Nov. 1995.
[23] J.-M. Lin, Y.-W. Chang, and S.-P. Lin, Corner sequence: A p-admissible °oorplan representation with a worst-case linear-time packing scheme," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 679{686, August 2003.
[24] J.-M. Lin and Y.-W. Chang, TCG: A transitive closure graph-based representation for non-slicing °oorplans," In Proceedings of the 38th Conference on Design Automation (DAC), pp. 764{769, June 2001.
[25] P.-N. Guo, C.-K. Cheng, and T. Yoshimura, An o-tree representation of non-slicing °oorplans and its application," In Proceedings of the 36th Conference on Design Automation (DAC), pp. 268{273, 1999.
[26] J. Cong and D. Pan, Interconnect estimation and planning for deep submicron design," In Proceedings of the 36th Conference on Design Automation (DAC), pp. 507{510, June 1999.
[27] S. Wilton and N. Jouppi, Cacti: An enhanced cache access and cycle time model," IEEE Journal of Solid-State Circuits, May 1996.
[28] S. Gupta, S. W. Keckler, and D. Burger, Technology independent area and delay estimates for microprocessor building blocks," Technical Report 2000-05, Department of Computer Sciences, The University of Texas at Austin, 2000.
[29] D. Brooks, V. Tiwari, and M Martonosi, Wattch: A framework for architectural-level power analysis and optimizations," In Proceedings of the 27th International Symposium on Computer Architecture (ISCA), June 2000.
[30] Hotspot tool suit," http://lava.cs.virginia.edu/HotSpot/.