(3.227.208.0) 您好!臺灣時間:2021/04/18 13:44
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:廖育德
研究生(外文):Yu-Te Liaw
論文名稱:使用於系統晶片中之兩階層式測試資料暨測試時間壓縮
論文名稱(外文):A Two-level Test Data Compression and Test Time Reduction Technique for SOC
指導教授:李建模
指導教授(外文):Chien-Mo Li
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:55
中文關鍵詞:測試資料壓縮測試時間壓縮系統晶片測試整合
外文關鍵詞:Test data compressionTest time compressionSoC test integration
相關次數:
  • 被引用被引用:0
  • 點閱點閱:104
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在單晶片系統日益成熟的紀元,巨大的測試資料量及極長的測試時間為其發展過程中所亟需克服的兩大問題。在本篇論文中,我們提出了一個單晶片系統層級中減低測試資料量及測試時間之兩階層式壓縮技巧。在第一階層中我們使用了選擇式霍夫曼編碼來對單晶片系統環境進行測試資料壓縮。於第二階層中我們藉由同時地廣播測試圖樣進入多個核心晶片來達成再一次的測試壓縮。最後我們使用d695為標的單晶片系統來進行實驗,得到了64%的測試資料壓縮及35%的測試時間壓縮。由於我們所提出的測試壓縮方法並不需要修改原有的核心晶片,因此非常適合使用於單晶片系統之整合。
In SOC era, long test time and large test data volume are two serious problems. In this thesis, a two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by selective-Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that the test data and test time are reduced by 64% and 35%, respectively. This technique requires no change of cores and hence provides a good SOC test integration solution for the SOC assemblers.
Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Introduction to the T2DaC 2
1.3 Contributions 3
1.4 Thesis Organization 4
Chapter 2. Back Ground and Previous Work 5
2.1 Previous Work 5
2.1.1 Data Compression Techniques 5
2.1.2 Linear Compression Techniques 7
2.1.3 Broadcasting Techniques 8
2.2 IEEE P1500 Standard 9
Chapter 3. T2 DaC 14
3.1 Hardware Architecture 14
3.2 L1 Decompression 15
3.3 L2 Adaptor 16
3.3.1 Single Core Session 18
3.3.2 Multiple Core Broadcast Session 18
3.3.3 Multiple Core Merge Session 20
3.4 Session Decision 21
3.5 L2 Compression Algorithm 22
3.5.1 MB Session Implementation 23
3.5.2 MM Session Implementation 24
3.6 L1 Compression 25
Chapter 4. Software Implementation 26
4.1 T2DaC Software Implementation 26
4.2 IEEE 1500 Wrapper Compiler Software Implementation 31
Chapter 5. Experimental Result 38
5.1 Test Data Reduction 38
5.2 Test Time Reduction 42
Chapter 6. Discussion and Future Work 44
6.1 Discussion 44
6.1.1 BIST 44
6.1.2 Traditional Broadcasting 44
6.2 Future Work 45
6.2.1 L1 rate adaptation 45
6.2.2 Iterative T2DaC 46
6.2.3 Exchanging Test Cube Columns 47
Chapter 7. Conclusion 48
References 49
[Bayraktaroglu 01] Bayraktaroglu, I., and A. Ogailoglu, “Test Volume and Application Time Reduction through Scan Chain Concealment,” Proc. of Design Automation Conference, pp. 151-155, 2001.

[Bayraktaroglu 03] Bayraktaroglu, I., and A. Ogailoglu, “Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression,” Proc. of VLSI Test Symposium, pp.113-118, 2003.

[Chandra 00] Chandra, A. and Chakrabarty, K., “Test Data Compression for System-on-a-Chip using Golomb Codes,” VLSI Test Symposium, pp. 113-120, 2000.

[Chandra 01] Chandra, A. and Chakrabarty, K., “Efficient Test Data Compression and Decompression for System-on-a-Chip Using Internal Scan Chains and Golomb Coding,” Design, Automation and Test in Europe, pp. 145-149, 2001.

[Chandra 03] Chandra, A. and Chakrabarty, K., “Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-length (FDR) Codes,” IEEE Transactions on Computers, Volume: 52, Issue: 8, pp. 1076-1088, 2003.

[Das 00] Das, D., and N.A. Touba, “Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns,” Proc. of International Test Conference, pp. 115-122, 2000.

[Hamzaoglu 99] Hamzaoglu, I., and J.H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Proc. of Int. Symposium on Fault Tolerant Computing, pp. 260-267, 1999.

[Hellebrand 95a] Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Trans. on Computers, Vol. 44, No. 2, pp. 223-233, 1995.

[Hellebrand 95b] Hellebrand, S., B. Reeb, S. Tarnick, and H.-J. Wunderlich, “ Pattern Generation for a Deterministic BIST Scheme,” Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 88-94, 1995.

[Hsu 01] Hsu, F.F. and Butler, K.M. and Patel, J.H., “A Case Study on the Implementation of the Illinois Scan Architecture,” Test Conference, pp. 538-547, 2001.

[Huffman 52] D. A. Huffman, “A Method for the Construction of Minimum Redundancy Codes,” in Proc. IRE, vol. 40, 1952, pp. 1098–1101.

[Ichihara 00] Ichihara, H., Kinoshita, K., Pomeranz, I. and Reddy, S.M., “Test Transformation to Improve Compaction by Statistical Encoding,” VLSI Design, pp. 294-299, 2000.

[Jas 98] Jas, A. and Touba, N.A., “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-based Designs,” Test Conference, pp. 458-464, 1998.

[Jas 99] Jas, A., J. Ghosh-Dastidar, and N.A. Touba, “Scan Vector Compression/Decompression Using Statistical Coding,” Proc. of IEEE VLSI Test Symposium, pp. 114-120, 1999.

[Jas 00] Jas, A., B. Pouya, and N.A. Touba, “Virtual Scan Chains: A Means for Reducing Scan Length in Cores,” Proc. of VLSI Test Symposium, pp. 73-78, 2000.

[Konemann 91] Konemann, B., “LFSR-Coded Test Patterns for Scan Designs,” Proc. of European Test Conf., pp. 237-242, 1991.

[Konemann 01] Konemann, B., “A SmartBIST Variant with Guaranteed Encoding,” Proc. of Asian Test Symposium, pp. 325-330, 2001.

[Krishna 01] Krishna, C.V., A. Jas, and N.A. Touba, “Test Vector Encoding Using Partial LFSR Reseeding,” Proc. of IEEE International Test Conference, pp. 885-893, 2001.

[Krishna 02] Krishna, C.V., and N.A. Touba, “Reducing Test Data Volume Using LFSR Reseeding with Seed Compression,” Proc. of IEEE International Test Conference, pp. 321-330, 2001.

[Krishna 03] Krishna, C.V. and Touba, N.A., “Adjustable Width Linear Combinational Scan Vector Decompression,” Computer Aided Design, pp. 863 - 866, 2003.

[Krishna 04] Krishna, C.V. and Touba, N.A., “3-stage Variable Length Continuous-flow Scan Vector Decompression Scheme,” VLSI Test Symposium, pp. 79-86, 2004.

[Lee 99] Kuen-Jong Lee and Jih-Jeen Chen and Cheng-Hua Huang, “Broadcasting Test Patterns to Multiple Circuits,” Computer-Aided Design of Integrated Circuits and Systems, pp. 1793-1802, 1999.

[Li 03] Li, L., and K. Chakrabarty, “Test Data Compression Using Dictionaries with Fixed-Length Indices,” Proc. of VLSI Test Symposium, pp. 219-224, 2003.

[Li 05] Yu Te Liaw, and James C.-M. Li, “A Two-level Test Data Compression and Test Time Reduction Technique for SOC,” 16th VLSI/CAD Technical Program, 2005.

[Lingappan 05] Lingappan, L., S. Ravi, A. Raghunathan, N. Jha, S. Chakaradhar, “Heterogeneous and Multi-level Compression Techniques for Test Volume Reduction in System-on-chip,” Proc., Int’l Conf. on VLSI Design, pp.187-193, 2005.

[Mitra 03] Mitra, S., and K.S. Kim, “XMAX: X-tolerant Architectures for Maximal Test Compression,” Proc. of International Conference on Computer Design, pp. 326-330, 2003.

[Rajski 02] Rajski, J., et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. of Int. Test Conf., pp. 301-310, 2002.

[Rao 03] Rao, W., I. Bayraktaroglu, and A. Orailoglu, “Test Application Time and Volume Compression through Seed Overlapping,” Proc. of Design Automation Conference, pp. 732-737, 2003.

[Reda 02] Reda, S., and A. Orailoglu, “Reducing Test Application Time through Test Data Mutation Encoding,” Proc. of Design, Automation, and Test in Europe, pp. 387-393, 2002.

[Reddy 02] Reddy, S., K. Miyase, S. Kajihara, and I. Pomeranz, “On Test Data Volume Reduction for Multiple Scan Chain Designs,” Proc. of VLSI Test Symposium, pp. 103-108, 2002.

[P1500] IEEE P1500 Standard for Embedded Core Test (SECT), IEEE Press, Piscataway, N.J., 2000; http://grouper.ieee.org/groups/1500/.

[Samaranayake 02] S. Samaranayake, N. Sitchinava, R. Kapur M. B. Amin, and T. W. Williams, “Dynamic Scan: Driving Down the Cost of Test,” IEEE Computers, pp. 65-70, Oct., 2002.

[Samaranayake 03] S. Samaranayake, and et. al., “A Reconfigurable Shared Scan-in Architecture,” Proc. IEEE VLSI Test Symp., pp. 9-14, 2003.

[Touba 98] Jas, A. and Touba, N.A., “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-based Designs,” Test Conference, pp. 458-464, 1998.

[Volkerink 02] Volkerink, E.H., A. Khoche, and S. Mitra, “Packet-based Input Test Data Compression Techniques,” Proc. of International Test Conference, pp. 154-163, 2002.

[Volkerink 03] Volkerink, E.H., and S. Mitra, “Efficient Seed Utilization for Reseeding Based Compression,” Proc. of VLSI Test Symposium, pp. 232-237, 2003.

[Wolff 02] Wolff, F.G., and C. Papachristou, “Multiscan-based Test Compression and Hardware Decompression Using LZ77,” Proc. of International Test Conference, pp. 331-339, 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文
 
1. 黃嘉雄(1999)。落實學校本位課程發展的行政領導策略。國民教育,40(1),29-34。
2. 顧瑜君(2005)。教師參與課程 以在地思考為出發的創意課程經營。教育研究,130,82-91。
3. 簡良平、甄曉蘭。(2001)學校自主發展課程之相關因素分析。教育研究集刊 ,46,43-80。
4. 鍾任琴(1994)。教師專業的探討。教師之友,35(5),29-35。
5. 陳鴻賢(2003)。 偏遠地區學校的發展與展望~古德曼的迷你學校。教育資料與研究,53,58-59。
6. 鄭淵全、蘇憶珊(2004)。學校特色課程發展與教學創新:掌聲之後的回顧。國教世紀,209,89-100。
7. 蔡清田(2002)。透過行動研究,實施九年一貫課程,進行學校本位課程發展。教育研究,93,53-58。
8. 楊冠政(1995)。環境教育發展史。教育資料集刊,20,1-34。
9. 黃政傑(1996)。從課程的角度看教師專業發展。教師天地,83,13-17。
10. 陳建銘(2004)。學校特色課程發展的問題與對策-以臺北市蓬萊國小的發展經驗為例。學校行政,34,138-149。
11. 張素貞(2004)。課程變革與教師專業成長。研習資訊,21(2),63-72。
12. 高新建(2002)。學校課程領導者的任務與角色探析。臺北市立師範學院學報,33,
13. 高新建(1999)。營造學校本位課程的發展的有利情境。教師天地,101,25-31。
14. 林佩璇(2000)。學校本位課程發展的背景探討。研習資訊,17(1),50-62。
15. 李子建(2003)。學校本位課程發展:理論與取向。課程與教學,6(3),105-128。
 
系統版面圖檔 系統版面圖檔