臺灣博碩士論文加值系統

隨著通訊系統的日益發展，高速傳輸系統的需求使得通訊電路面臨設計上和製程上的挑戰，為了與基頻數位類比混合式電路作整合，同時達到低功率消耗以及低成本的要求，採用CMOS為製程的高速電路已成為近年來的研究趨勢。
多相位震盪器是現代通訊系統中不可或缺的一部分，在本論文中，我們將針對多相位震盪器進行介紹並加以實現。內容可以分成為兩大部分，第一部分主要介紹震盪器的一些基本概念。為了因應高速傳輸的需求；第二部分中，我們將提出多種新型高速多相位震盪器的架構．
本論文的章節安排如下：第一章主要描述多相位震盪器在通訊系統中的重要性；第二章將震盪器的基本原理和元件特性進行探討；第三章整理現今多相位訊號的實現方法；第四章我們以台積電CMOS 0.18-μm製程，實現一個9-GHz的正交壓控震盪器，並提出以切換式偏壓來改善相位雜訊；第五章將呈現一個15-GHz/30-GHz的雙頻多相位壓控震盪器，以及多相位的驗證方式；最後，第六章中，我們實現了一個操作在43-GHz的新型多相位壓控震盪器，所產生的多相位訊號符合光纖通訊OC-768系統所需的規格。

The rapid growth of optical communication markets has motivated the development of high data-rate transceivers. In order to be integrated with the baseband mixed-mode circuits and to achieve the requirements of low power and low cost, utilizing the complementary metal-oxide semiconductor (CMOS) technology has become the design trends.
Among the circuits of the communication systems, multi-phase voltage-controlled oscillators (VCOs) are essential building blocks. The thesis will focus on the design of high-speed multi-phase VCOs using CMOS technologies.
The details of the thesis are organized as followed. In chapter 1, the applications of multi-phase VCOs in communication systems will be illustrated. The fundamentals of the oscillators from theories and circuit elements will be presented in chapter 2. Different kinds of multi-phase generators will be discussed in chapter 3. In chapter 4, a 9-GHz quadrature-phase VCO with a switched-bias technique is realized in TSMC CMOS 0.18-μm technology. In chapter 5, a 15-GHz/30-GHz dual-band multi-phase VCO with a phase error verification module is presented. Finally, a novel 43-GHz multi-phase VCO, which is suitable for the applications in the OC-768 optical communication systems, will be demonstrated in chapter 6.

Acknowledgements
Abstracts
Table of Contents
List of Figures
List of Tables
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 3
Chapter 2 Oscillator Fundamentals 5
2.1 Oscillator Origins 5
2.2 Circuit Components 7
　 　2.2.1 MOS Device Physic 7
　 　2.2.2 Quality Factor 9
　　 2.2.3 Inductor 10
　　 2.2.4 Varactor 12
　　 2.2.5 Transmission Line 13
2.3 Phase Noise 16
　　 2.3.1 Noise Source 16
　 　2.3.2 Phase Noise Model 18
　 　2.3.3 Relation between Phase Noise and Jitter 23
Chapter 3 VCO Architectures 25
3.1 Overview 26
3.2 Basic LC-Tank VCO 27
3.2.1 Filter LC-tank VCO 28
3.2.2 Switched-bias VCO 28
3.2.3 Multi-Phase Generation 29
3.3 Active-Coupling VCO 31
3.4 Ring Oscillator 34
3.4.1 Resistor Load 34
3.4.2 Transistor Load 35
3.4.3 Inductive Load 35
3.5 Traveling Wave VCO 37
3.5.1 Distributed VCO 37
3.5.2 Rotary-Traveling-Wave VCO 39
Chapter 4 A 9-GHz Quadrature-phase VCO 41
4.1 Motivation 41
4.2 Circuit Design 42
4.2.1 Design of the Cross-Coupled VCO 42
4.2.2 Quadrature-Phase VCO with Active Coupling Pair 44
4.3 Phase Error Verification 45
4.3.1 The Built-In-Self-Test (BIST) Module 45
4.3.2 The Effects of Different Kinds of Phase Errors 46
4.4 Experimental Results 49
4.4.1 Die Photo 49
4.4.2 Measurement Setup 49
4.4.3 Measurement Results 51
4.5 Conclusions 56
Chapter 5 A 15-GHz/30-GHz Dual-Band Multi-Phase VCO 57
5.1 Motivation 57
5.2 Circuit Design 60
5.2.1 The Dual-Band Multi-Phase VCO 60
5.2.2 The Built-In-Self-Test (BIST) Module 61
5.3 Experimental Results 64
5.3.1 Die Photo 64
5.3.2 Measurement Setup 64
5.3.3 Measurement Results 66
5.4 Conclusions 71
Chapter 6 A 43-GHz Muilti-Phase VCO 73
6.1 Motivation 73
6.2 Introduction 75
6.3 Circuit Design 76
6.4 Simulation Results 82
6.4.1 Traveling Path 82
6.4.2 Compensation Inductor 82
6.4.3 Output Matching 83
6.4.4 DC Path 84
6.5 Measurement Considerations 88
6.5.1 Layout 88
6.5.2 Measurement Setup 89
6.6 Conclusions 90
Conclusions 91
Bibliography 93

[1] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.
[2] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE Journal of Solid-State Circuits, Vol. 36, pp. 761-768, May 2001.
[3] J. E. Rogers and J. R. Long, “A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS,” IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1781-1789, Dec. 2002.
[4] J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18-/spl mu/m CMOS technology,” IEEE Journal of Solid-State Circuits, Vol. 38, pp. 2181-2190, Dec. 2003.
[5] “The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH),” ITU-T, Recommendation G.825, 2000.
[6] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, 1998
[7] S. Emami et al., ”Large-Signal Millimeter-Wave CMOS Modeling with BSIM3,” Radio Frequency Integrated Circuits Symposium, 2004.
[8] C. H. Doan et al., “Millimeter-Wave CMOS Design,” IEEE Journal of zSolid-State Circuits, Vol. 40, pp. 144-155, Jan. 2005.
[9] T. Soorapanth et al., “Analysis and Optimization of Accumulation-Mode Varactor for RF ICs,” Symposium in VLSI circuits Digest of Technical Papers, 1998.
[10] K. Molnar, “MOS varactor modeling with a subcircuit utilizing the BSIM3v3 model,” Transactions on Electron Devices, Vol. 49, pp. 1206-1211, July 2002.
[11] D. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” Proc. IEEE, Vol. 54, pp. 329-330, Feb. 1996.
[12] A. Hajimiri and T. H. Lee, “A general Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid-State Circuits, Feb. 1998.
[13] A. Hajimiri et al., “Jitter and Phase Noise in Ring Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 34, pp. 790-804, June 1999.
[14] A. Rofougaran et al., “A 900MHz CMOS LC-Oscillator with Quadrature Outputs,” IEEE Conference of Solid-State Circuits, 1999.
[15] M. Tiebout, “Low-Power Low-Phase-Noise Differentially Tuned quadrature VCO Design in Standard CMOS,” IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1018-1024, July 2001.
[16] R. Aparicio et al., “A Noise-Shifting Differential Colpttis VCO,” IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1728-1736, Dec. 2002.
[17] P. Andreani et al., “Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO,” IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1737-1747, Dec. 2002.
[18] S. Li et al., “A 10-GHz CMOS Quadrature LC-VCO for Multirate Optical Applications,” IEEE Journal of Solid-State Circuits, Vol. 38, pp. 1626-1634, Oct. 2003.
[19] “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE Journal of Solid-State Circuits, Vol. 38, pp. 1626-1634, Oct. 2003.
[20] D. Baek et al., “8-GHz CMOS quadrature VCO using transformer-based LC tank, Microwave and Wireless Components Letters, IEEE, Vol. 13, pp. 446-448, Oct. 2003
[21] H. R. Kim et al., “A Vary Low-Power Quadraure VCO with Back-Gate Coupling,” IEEE Journal of Solid-State Circuits, Vol. 39, pp. 952-955, June 2004.
[22] L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltage controlled ring oscillator based on three-stage subfeedback loops,” in Proc. Int. Symp. Circuits and Systems, Vol. 2, pp. 176–179, 1999
[23] Y. A. Eken et al., “A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18-_m CMOS,” IEEE Journal of Solid-State Circuits, Vol. 39, pp. 230-233, Jan. 2004.
[24] H. Wu and A. Hajimiri, "Silicon-Based Distributed Voltage-Controlled Oscillators," IEEE Journal of Solid-State Circuits, Vol. 36, March 2001.
[25] J. Wood et al., "Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology," IEEE Journal of Solid-State Circuits, Vol. 36, Nov. 2001.
[26] L. Mercey et al., “A 18GHz rotary traveling wave VCO in CMOS with I/Q outputs,” ESSCIRC, pp. 489-492, Sept. 2003.
[27] E. Hegazi et al., “A Filtering Technique to Lower LC Oscillator Phase Noise,” IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1921-1930, Dec. 2001.
[28] E. Klumperinket al., “Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing,” IEEE Journal of Solid-State Circuits, Vol. 35, pp. 994-1001, July 2000.
[29] H. Tian, “Analysis of 1/f Noise in Switched MOSFET Circuits,” IEEE Transactions on Circuits and Systems, Vol. 48, pp. 151-157, Feb. 2001.
[30] C. C. Boon et al., “RF CMOS Low-Phase-Noise LC Oscillator through Memory Reduction Tail Transistor,” IEEE Transactions on Circuits and Systems, Vol. 51, pp. 85-89, Feb. 2004.
[31] F. Behbahani et al., “CMOS Mixers and Polyphase Filters for Large Image Rejection,” IEEE Journal of Solid-State Circuits, Vol. 36, pp. 873-887, June 2001.
[32] J. J. Kim and B. Kim, “A Low-Phase-Noise CMOS LC Oscillator with a Ring Structure,” IEEE Conference of Solid-State Circuits, 2000.
[33] M. Vanmackelberg et al., “90nm SOI-CMOS of 150GHz fmax and 0.8dB NFmin @6GHz for SOC,” IEEE Int. SOI Conference, pp. 153-154, Oct. 2002.
[34] D. Yamazaki et al., “A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol.1, pp. 240–525, Feb. 2004.
[35] T. Yamamoto et al., “A 43Gb/s 2:1 selector IC in 90nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol.1, pp. 238 – 239, Feb. 2004.
[36] P. Hazucha et al., “A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS,” Symposium on VLSI Circuits Dig. Tech. Papers, pp. 256–257, June 2004.
[37] W. Jeamsaksiri et al., “Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA,” Symposium on VLSI Circuits Dig. Tech. Papers, pp. 100–101, June 2004.
[38] G. Agrawal, Fiber-Optica Communication Systems, Wiley Inter-Science, 2002.
[39] D. K. Shaeffer et al., “Performance-Optimized Microstrip Coupled VCOs for 40-GHz and 43-GHz OC-768 Optical Transmission,” IEEE Journal of Solid-State Circuits, Vol. 38, pp. 1130-1138, July 2003.
[40] W. F. Andress and D. Ham, “Standing Wave Oscillators Utilizing Wave-Adaptive Tapered Transmission Lines,” IEEE Journal of Solid-State Circuits, Vol. 40, pp. 638-651, March 2005.
[41] W. F. Andress and D. Ham, “A Circular Standing Wave Oscillator,” IEEE Conference of Solid-State Circuits, 2004.