網際網路與多媒體服務需求的增加(如數位電視)帶動了高速光纖通訊系統蓬勃的發展。具百億位元傳輸率的STM-64(OC-192)與具四百億位元傳輸率的STM-256(OC-768)為目前光纖通訊系統的主流。而近年來，不斷進步的深次微米互補式金氧半導體技術已具相當於高速III-V族元件的高頻特性而逐漸應用在高速電路設計。其低成本與高整合性的優點較高成本的III-V族更適於消費性電子的製造。本篇論文以0.18微米互補式金氧半導體技術實現了一個適用於百億位元傳輸率的可調式轉阻放大器及一個具45.6兆赫茲頻寬的矩陣分散式放大器。
本可調式轉阻放大器採用regulated cascode (RGC)輸入緩衝級, shunt-peaking技巧及電壓-電流回授組態，並且使用可變回授及負載電阻，可在2.2伏特跨壓下有45~52dBΩ的轉阻增益調整範圍與7~10兆赫茲的頻寬調整範圍。全部功率消耗(含輸出緩衝級)為32毫瓦。晶片大小為0.83x0.66平方公厘。
而獨特的矩陣分散式放大器採用一個2x4的矩陣結構。在這個電路中使用了交錯式中間傳輸線架構及疊接組態的增益級以增進放大器的增益及頻寬。而所有電感均用最佳化的共平面波導結構實現。在497 毫瓦的功率消耗下具有6.7 dB的增益與45.6兆赫茲的頻寬。晶片尺寸為1.8x1.05平方公厘。

The increasing popularity of internet and multimedia communication (digital TV) services has motivated the development of high-speed optical communication system. Commercial STM-64 (OC-192) operating near 10Gb/s and STM-256 (OC-768) operating near 40Gb/s are the main streams today. In recent years, the deep submicron CMOS technology has competitive high-frequency characteristics with high-speed Ⅲ-Ⅴ devices and is gradually used in high-speed circuits. The lower cost and higher level of integration make it more attractive than high-cost III-V technology for commercial use. In this thesis, a 10-Gb/s tunable transimpedance amplifier (TIA) and a 45.6-GHz matrix distributed amplifier are implemented in a standard 0.18-μm CMOS process.
The tunable TIA incorporates a regulated cascode (RGC) input buffer, shunt-peaking technique, voltage-current feedback topology and the applications of variable feedback and load resistors to achieve a 45~52-dBΩ tuning range of transimpedance gain and a 7~10-GHz tuning range of bandwidth at a 2.2-V supply voltage. Total power consumption including output buffer is 32 mW. The whole chip size is 0.83 x 0.66 mm2.
The novel matrix distributed amplifier employs a 2x4 matrix architecture. The proposed circuit adopts interleaving-central-line architecture and cascode gain stages for gain and bandwidth enhancement. Optimized CPW is used to implement the required inductors. With a power consumption of 497mW, a gain of 6.7 dB and a 3-dB bandwidth of 45.6 GHz are measured. The whole die size is 1.8x1.05 mm2.

Acknowledgements
Abstracts Ⅰ
Table of Contents Ⅴ
List of Figures Ⅶ
List of Tables Ⅸ

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 6
Chapter 2 Optical Communication System Background and
Requirements 7
2.1 Introduction of Optical Communication System 7
2.2 Basic Concepts 8
2.2.1 Date Rates 9
2.2.2 NRZ Data Format 9
2.2.3 Receiver Sensitivity and Bit Error Rate (BER) 9
2.2.4 Eye Diagram 11
2.3 Design Considerations of Broadband Amplifier
Bandwidth in Optical Communication System 13
2.3.1 Effect of Bandwidth Limitation on Eye Diagram 13
2.3.2 Tradeoff of Bandwidth between Noise and ISI 14

Chapter 3 Design of 10-Gb/s CMOS Tunable Transimpedance
Amplifier 18
3.1 Introduction 18
3.2 Proposed Tunable Transimpedance Amplifier 21
3.2.1 Regulated Cascode Input Current Buffer 21
3.2.2 Tunable Transimpedance Amplifier 23
3.3 Experimental Results 25
3.3.1 S-parameter Measurement 25
3.3.2 Eye Diagram Measurement 29
3.3.3 Performance Summary 31
3.3.4 Discussion 32
3.4 Revised Tunable Transimpedance Amplifier 34
3.4.1 Circuit Design 35
3.2.2 Simulation Results 37
3.4.3 Performance Summary 38
3.5 Conclusion 39

Chapter 4 Design of 45.6-GHz CMOS Matrix Distributed
Amplifier 40
4.1 Introduction 40
4.2 Basic Principle of Conventional CMOS Matrix
Distributed Amplifiers 41
4.3 Proposed Matrix Distributed Amplifier 46
4.3.1 Circuit Design 46
4.3.2 Device Selection 49
4.3.3 Cascode Gain Cell Design 52
4.3.4 Coplanar Waveguide Inductor Design 55
4.4 Experimental Results 58
4.4.1 S-parameter Measurement 58
4.4.2 Eye Diagram Measurement 61
4.4.3 Discussion 62
4.5 Performance Summary 64

Chapter 5 Conclusion 66

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