臺灣博碩士論文加值系統

在本篇論文中，提出一個適用於IEEE 802.11 a無線區域網路系統之實虛部不對稱自我校準演算法。此演算法是在開機時由基頻接收機量測一連串的單頻信號來達到，而此單頻信號的頻率是傳送機所傳送之單頻信號頻率的兩倍。在實際的資料傳送時，剩下的實虛部不對稱量也會被繼續追蹤。因此，對於無線區域網路系統的射頻前端之要求可以大大的放寬。此外，藉由所提出的演算法，即使在傳送機和接收機都有 ±5% 的增益不對稱、 ±5˚ 的相位不對稱以及 ±232仟赫茲的載波頻率偏移的情況下，信噪比的損失也會小於0.5dB。
接下來是先由C++建立802.11a的基頻系統模型，包含浮點數及定點數模擬。再根據硬體化的定點數模擬來寫Verilog RTL程式，此外，由Simplify Pro 7.3做合成以及QuartusII 3.0來做電路的放置及繞線，然後整個IEEE 802.11的基頻收發機由Altera Stratix EP1S80 DSP板操作在40MHz來實現，總共使用了約32000個邏輯單元。最後，整個系統的量測是由Tetronix TLA 715的樣本產生器及邏輯分析儀來達到。

Based on the single tone power evaluation (STPE), a self-calibration algorithm of I/Q mismatch is proposed for the IEEE 802.11a WLAN systems. The self-calibration algorithm is performed by the digital baseband at transceiver start-up to measure the signal power of the single tone signal, which is located at the double frequency band at the receiver. Furthermore, the residual I/Q mismatch is tracked during the physical data transmission. Therefore, the design requirements of the RF front-end for the WLAN OFDM transceiver are alleviated. According to the proposed algorithm, the residual signal-to-noise ratio (SNR) degradation is totally less than $0.5$-dB with $pm5 \%$ gain mismatch ($Delta G$) and $pm5^circ$ phase mismatch ($Delta heta$) in the transmitter and receiver respectively, and carrier frequency offset (CFO $=pm232$kHz).

The system simulation of the IEEE 802.11a WLAN baseband transceiver is modeled by C++. Furthermore, it consists of 2-phase, floating and fixed point. The hardware-like fixed-point simulation, which considers the finite word length effect, is used to develop the Verilog RTL code. Besides, the Simplify Pro 7.3 and QuartusII 3.0 are used to synthesis and place and route of the Verilog RTL respectively. Moreover, the prototype of the IEEE 802.11a WLAN baseband transceiver is realized by Altera Stratix EP1S80 DSP development board with about 32000 logic elements at 40MHz. Finally, the system evaluations are measured by Tektronix TLA715 pattern generator and logic analyzer.

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Basic Principles of OFDM and IEEE 802.11a Standard 3
2.1 OFDM Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Overview of OFDM . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 OFDM Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 Typical OFDM Transceiver . . . . . . . . . . . . . . . . . . . . . 9
2.2 Features of IEEE 802.11a Standard . . . . . . . . . . . . . . . . . . . . . 10
3 Wireless Channel Model and Transceiver Design 17
3.1 Wireless Channel Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Power Amplifier Nonlinearity . . . . . . . . . . . . . . . . . . . . 20
3.1.2 Power Delay Profile (PDP) . . . . . . . . . . . . . . . . . . . . . . 20
3.1.3 Rayleigh Fading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.4 Carrier Frequency Offset (CFO) . . . . . . . . . . . . . . . . . . . 23
3.1.5 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.6 I/Q Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.7 DC Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.8 Timing Frequency Offset (TFO) . . . . . . . . . . . . . . . . . . . 32
3.2 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1 Delay Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.2 Matched Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2.3 Carrier Recovery (CR) Loop . . . . . . . . . . . . . . . . . . . . . 40
3.2.4 Timing Recovery (TR) Loop . . . . . . . . . . . . . . . . . . . . . 42
3.3 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Calibration Algorithm and Architecture of the I/Q Mismatch 47
4.1 Coarse Calibration Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Fine Calibration Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.1 Frequency Domain Approach . . . . . . . . . . . . . . . . . . . . 54
4.2.2 Time Domain Approach . . . . . . . . . . . . . . . . . . . . . . . 56
4.3 Calibration Timing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 FPGA Implementation 61
5.1 Introduction to FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 FPGA Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 FPGA Implementation Platform . . . . . . . . . . . . . . . . . . . . . . . 63
5.4 Transceiver Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.4.1 Complex Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.4.2 Arc Tangent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.4.3 I/Q Mismatch Compensation and Pre-Compensation Circuits . . 68
5.4.4 Matched Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.5 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6 Conclusion 79
A Synplify Pro 81
A.1 Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
B Quartus II 87
B.1 Quartus II 3.0 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 87
C PG and LA 97
C.1 Acute PG and LA Instructions . . . . . . . . . . . . . . . . . . . . . . . 97

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