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研究生:紀達聖
研究生(外文):Ta-Sheng Chi
論文名稱:互補式金氧半雙迴路頻率合成器之設計與實作
論文名稱(外文):Design and Implementation of CMOS Dual-Loop Frequency Synthesizers
指導教授:呂良鴻
指導教授(外文):Liang-Hung Lu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:60
中文關鍵詞:頻率合成器鎖相迴路雙迴路直接數位合成
外文關鍵詞:frequency synthesizerPLLdual-loopDDS
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近幾年,無線通訊的長足進步已逐漸取代有線傳輸成為現今最無可取代的通訊模式。急速成長的無線區域網路市場也極力的帶動高傳輸速率與傳輸量的需求。

在本論文裡,我們呈現了以無線通訊為取向,操作在2.4GHz頻帶,以雙迴路架構為基礎的頻率合成器。第一顆晶片包含相位頻率偵測器(PFD),電荷幫浦(CP),壓控振盪器(VCO),混波器(Mixer),以及多除數除法器。低通濾波器的部份由外接元件所實現。相較於傳統的整數位頻率合成器,此單晶雙迴路頻率合成器能在相位雜訊(phase noise)、頻道間隔(channel spacing)、參考頻率(reference frequency)和穩定延遲時間(settling time)之間取得較佳的取捨。

第二顆晶片也是以雙迴路為基礎。不同的是,其用來產生偏移頻率(offset frequency)的迴路,由直接數位頻率合成器(direct digital synthesizer)來取代。直接數位頻率合成器的使用,使得此頻率合成器能適用於直接頻率調變(direct frequency modulation),而不需要使用在分數型頻率合成器用到的預強調(pre-emphasis)和數位校正迴路(digital calibration loop)等技巧。
Wireless communication has undergone an incredible development over last few years, and it''s gradually replacing the cable communication to become the most important part of the modern world. The growing wireless LAN market has generated increasing interest in technologies enabling higher data rates and capacity than initially deployed systems.

The dual-loop type frequency synthesizers for wireless
applications are presented in this thesis. The first chip is
composed of phase frequency detector (PFD), charge pump (CP),
LC-tank voltage-controlled oscillator (VCO), and ring-type
voltage-controlled oscillator, single-sideband mixer (SSB mixer), and multi-modulus driver. The required low-pass filter is provided by off-chip components in this design. The synthesizer employs a dual-loop architecture to realize a monolithic design with more optimal trade-off among phase noise, channel spacing, reference frequency and settling time compared to the conventional integer-N phase-locked loop architecture.

The architecture of the second chip is based on dual-loop type synthesizer. However, the offset frequency is generated by a direct digital synthesizer. The use of the DDS makes this synthesizer potentially suitable for direct frequency modulation, without requiring any pre-emphasis and digital calibration loop that are instead necessary in fracional-N PLL.
Contents
Contents i
List of Figures iii
List of Tables vi
Acknowledgements vii

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2 Synthesizer Background 3
2.1 General Consideration 3
2.1.1 Phase Noise and Sidebands 3
2.1.2 Settling Time 6
2.2 Basic Building Blocks of PLL 7
2.2.1 Phase Frequency Detector (PFD) 7
2.2.2 Charge Pump 8
2.2.3 Loop Filter 9
2.2.4 Voltage-Controlled Oscillator 11
2.3 Mathematical model of PLL for the locked state 12
2.4 Phase noise in PLLs 15
2.4.1 Noise at input 16
2.4.2 Phase noise of VCO 17

Chapter 3 Realization of CMOS Dual-Loop Frequency Synthesizer 18
3.1 Architecture of Dual-Loop Frequency Synthesizer 18
3.2 Phase Frequency Detector (PFD) 22
3.3 Charge Pump and Loop Filter 24
3.4 Frequency Divider 25
3.5 Ring-type Voltage-Controlled Oscillator 28
3.6 Quadrature Voltage-Controlled Oscillator (QVCO) 31
3.7 Single-Sideband Mixer (SSB Mixer) 33
3.8 Summary 33

Chapter 4 Realization of a DDS-Based PLL for 2.4-GHz Frequency Synthesis 37
4.1 Fundamentals of DDS Technology 38
4.1.1 DDS Overview 38
4.1.2 DDS Block Diagram 38
4.1.3 Comparison of DDS and PLL 41
4.2 Architecture of DDS-based PLL for Frequency Synthesis 43
4.3 Voltage-Controlled Oscillator 45
4.4 Charge Pump 45
4.5 SSB Mixer 47
4.6 Frequency Divider 48
4.7 Summary 50

Chapter 5 Experiment Results 52
5.1 Testing Setup 52
5.2 PLL Measurement 55
5.3 Discussions of the Measurement Results 58

Chapter 6 Conclusion 59

Bibliography 60
[1] T. Aytur and J. Khoury, Advantages of dual-loop frequency synthesizers for GSM applications, in Proc. IEEE Int. Symp. Circuits and Systems, 1997.
[2] T. K. K.Kan, G. C. T.Leung, and H. C.Luong, A 2-V 1.8-GHz fully integrated CMOS dual-loop frequency synthesizer, IEEE J. Solid-State Circuits, vol. 37, pp.1012-1020, Aug. 2002.
[3] C. Lam and B. Razavi, A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4um CMOS technology, IEEE J. Solid-State Circuits, vol. 35, pp. 788-794, May 2000.
[4] B.Razavi, RF Microelectronics Upper Saddle River, NJ: Prentice-Hall, 1998.
[5] Roland E. Best, Phase-Locked Loops, 5e, MaGRAW-HILL, 2003.
[6] W. S. T.Yan and H. C.Luong, A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator, IEEE Trans. Circuits Syst. II, vol. 48, pp. 216-221, Feb 2001.
[7] A. Hajimiri and T. H. Lee, Design issues in CMOS differential LC oscillators, IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, Feb. 1999.
[8] A. Bonfanti, F. Amorosa, C. Samori, and A. L. Lacaita, A DDS-Based PLL for 2.4-GHz Frequency Synthesis, IEEE Transactions on Circuits and Systems XII: Analog and Digital Signal Processing, Vol. 50, No. 12, Dec. 2003.
[9] Pascal Nelson, Considerations in RF Synthesis V PLL and DDS Together, Communications Design Conference, 2003.
[10] A. R. Karl, A 2.4GHz Frequency Synthesizer in 0.6um CMOS, MS thesis, Dept.of Electrical Engineering, University of Califoria Los Angeles, Mar. 1998.
[11] T. H. Lee and Ali Hajimiri, Oscillator phase noise: a tutorial IEEE J. Solid-State Circuit, vol.35, pp.326-336, Mar.2000.
[12] J. Yuan and C. Svensson, High-Speed CMOS Circuit Techinique, IEEE J. Solid-State Circuits, vol.24, pp.62-70, Feb. 1989.
[13] MIT Open Courseware, High Speed Communication Circuits and Systems, Spring 2003.
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