臺灣博碩士論文加值系統

在GSM手機通訊標準中，調變信號的方式是GMSK。它是一種連續相位的調變方式，為GFSK的一種。在本論文的研究中，建立了一套使用Simulink的相位調變器行為模型來探討他頻率及spectrum。在晶片中使用一個三角積分調變除小數頻率合成器來實現部分相位調變器的射頻電路。其中相位頻率比較器、電流泵、多模數除頻器及壓控震盪器是用0.35μm混和信號 2P4M CMOS製程的積體電路實現,而三角積分調變器是由 MATLab 通過 pattern generator 來實現。

In GSM communication system, the modulation of the modulated signals are GMSK. It is a kind of modulation way of continuiing phase, a kind of GFSK modulation way. In this work, we set up a complete behavior model of phase modulator in Simulink environment. In this chip, we use a sigma-delta fractional-N frequency synthesizer to implement partial RF circuit of the phase modulator. A phase frequency detector, a charge pump ,a multi-modulus divider and a voltage-controlled oscillator are fabricated with 0.35μm 2P4M CMOS technology and are operated over 1.8 GHz. The sigma-delta modulator is implemented by Simu-link and the pattern generator.

Table of Contents



Table of Contents I
List of Figures V
List of Tables XI


Chapter 1 Introduction 1
1.1 Motivation and Research Goals 1
1.2 Thesis Overview 2

Chapter 2 Basic Concepts and System Overview 3
2.1 Modulators 3
2.1.1 Areas of Focus 3
2.1.2 Modulator Architectures 4
2.2 Phase-locked Loops 6
2.2.1 Basic Topology 6
2.2.2 PLL’s Linear Models 8
2.2.3 PLL’s Basic Components 13
2.2.4 Noise in the PLL 16
2.3 Frequency Synthesizers 20
2.3.1 Frequency Multiplication and Integer-N Frequency Synthesizers 20
2.3.2 Fractional-N PLL 22
2.4 Sigma-Delta Modulation on Fractional-N PLL 26
2.4.1 Quantization Noise of Sigma-Delta Modulators 28
2.4.2 High Order Sigma-Delta Modulators 29
2.4.3 Multi-Stage Noise Shaped (MASH) Structure 30

Chapter 3 Gaussian Minimum Shift Keying Background and GMSK Modulators 33
3.1 Frequency Plan 33
3.2 Modulation Format 35
3.2.1 MSK Modulation 35
3.2.2 Gaussian MSK (GMSK) 37
3.3 The Challenge of Achieving High Data Rates and Low Noise 41

Chapter 4 Behavioral Models of Sigma-Delta Fractional-N PLL 47
4.1 Integer-N and Fractional-N PLL Behavior Simulations 47
4.1.1 Integer-N PLL 48
4.1.2 Fractional-N PLL 49
4.2 Simulations of Fractional-N Modulated by Sigma-Delta GMSK 51
4.2.1 Sigma-Delta Simulations 51
4.2.2 GMSK Simulations 54
4.2.3 Sigma-Delta GMSK Fractional-N PLL 55

Chapter 5 Circuit Implementation of Building Blocks and Components 61
5.1 Phase Frequency Detector 61
5.2 Charge Pump 63
5.3 Low-Pass Filter 64
5.4 Voltage-Controlled Oscillator 67
5.4.1 MOS Varactors 67
5.4.2 Inversion-Mode MOS Varactors 68
5.4.3 Voltage-Controlled Oscillator Design 69
5.5 Programmable Dividers 70
5.5.1 Architecture Approaches 70
5.5.2 Type-I of the Prescalers 73
5.5.3 Type-II of the Prescalers 79

Chapter 6 Simulation Results 83
6.1 The Circuit Pre-Simulations of the PLL 83
6.1.1 The Pre-Simulations of PFD and CP 83
6.1.2 The Pre-Simulations of the Voltage-Controlled Oscillator 85
6.1.3 The Pre-Simulations of the Prescalers 87
6.2 The Circuit Post-Simulations of the PLL 88
6.2.1 The Post-Simulations of PFD and CP 88
6.2.2 The Post-Simulations of the Voltage-Controlled Oscillator 90
6.2.3 The Post-Simulations of the Prescalers 91
6.2.4 The Post-Simulations of the Close Loop 92

Chapter 7 Measure Results and Conclusions 95
7.1 Measure Results and Discussion 95
7.1.1 Testing Setup 95
7.1.2 Chip Measurement 96
7.1.3 Discussion of the Chips 98
7.2 Conclusions 99
7.3 Appendix 99
7.3.1 The Ratiocination of the Chip Measurement Results 99
7.3.2 The Optimum of the Design Issues 100
7.3.3 The Comparisons between fractional-N PLL and integer-N PLL 106
7.3.4 The Working Mode of the PMOS Varactor 108
7.3.5 The Working Mode of the Charge Pump Circuit 109

Bibliography 111

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