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研究生:蔡勝中
研究生(外文):Sheng-Chung Tsai
論文名稱:全數位式鎖相迴路之設計與實作
論文名稱(外文):Design and Implementationof an All Digital Phase Lock Loop
指導教授:陳少傑陳少傑引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:54
中文關鍵詞:全數位式鎖相迴路
外文關鍵詞:ADPLLDCO
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ABSTRACT

In this Thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. A 16-bit digitally controlled CMOS oscillator uses a 4-stage ring of a modified differential delay cell. The DCO uses the even-stage skew dual-delay path scheme [11], which enables higher operating frequency. The frequency search and the phase tracking are major blocks in a control unit. We use a high sensitivity phase tracking and frequency search algorithm, which consists two D-type flip flop and some logical circuits.
In our proposed ADPLL, we implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in the TSMC 0.18μm 1P6M technology. The supply voltage is 1.8V. The simulation results show that when DCO operates at 2.4GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 30 reference clock cycles (algorithm). The lock-in range is 2.07GHz to 2.56GHz. The power consumption is 106.1mW at 2.4GHz.
TABLE OF CONTENTS


ABSTRACT ……..…………………………………………………………… i
LIST OF FIGURES …………………………………………………………... v
LIST OF TABLES ……..……………………………………………………… ix
1 INTRODUCTION …………………………………………………………. 1
1.1 Background …………..…………………….………………………... 1
1.2 Motivation ............................................................................................ 2
1.3 Thesis Organization …….………………………………………..….. 3
2 CLASSIFICATION OF PLL TYPES …..………………………………… 5
2.1 Linear PLL ….….……………………………………………………. 6
2.2 Digital PLL .………..….……………………………………………… 7
2.3 All digital PLL .……………………………………………………… 9
2.4 Comparison ……..………………………….………………………… 10
3 ANALYSIS OF ADPLL ARCHITECTURE ……………………………… 13
3.1 Architecture Introduction ……..……………………………………… 13
3.2 Digitally Controlled Oscillator ……..………………………………… 14
3.3 Mode of Operation in an ADPLL ………..…………………………… 16
3.3.1 Frequency Acquisition …….…..……………………………… 16
3.3.2 Phase Acquisition ….....………………………..……………... 20
3.3.3 Phase and Frequency Maintenance ……..……..……………. 24
4 CRITICAL MODULES IN AN ADPLL ARCHTECTURE …….……… 25
4.1 Phase and Frequency Detector ………………………..……………… 25
4.2 Digitally Controlled Oscillator ……………………………………..… 29
4.3 Summary …….……………………..………………………….……… 32

5 DESIGN AND IMPLEMENTATION ………………………………..…… 33
5.1 Introduction to System Architecture ……..………………………… 33
5.2 Digital of High Sensitivity Phase and Frequency Detector ………..… 34
5.3 Design a Higher Operation Frequency of DCO …..………………… 36
5.4 Control Unit ………………………………………………………..… 41
5.4.1 Frequency Search ………………..…………………………… 41
5.4.2 Phase Tracking ………………….………………………..… 44
5.4.3 Signal Control Unit ….……………..……………..………… 45
5.5 Simulation and Implementation Result ……......……………………. 46
6 CONCLUSION ……………………………………..……………………… 51
REFERENCE ……………………………………………..……………………. 53
REFERENCE

[1]R. E. Best, Phase-Locked Loop: Design, Simulation, & Applications, Fourth Edition, McGraw- Hill Inc., 1993.
[2]J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital phase- locked loop with 50-cycle lock time suitable for high-performance microprocessors,” IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr. 1995.
[3]J.-S. Chiang and K.-Y. Chen, “The design of an all-digital phase- locked loop with small DCO hardware and fast phase lock,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 7, pp. 945-950, Jul 1999.
[4]許騰尹, “The Study of All Digital Phase-Locked Loop (ADPLL) and its Applications,” PHD Thesis, National Chiao Tung University, Sep 1999.
[5]鄭吉成, “The Analysis and Design of All-Digital Phase Loop Lock (ADPLL),” Master Thesis, National Chiao tung University, Jul 2001.
[6]C.-C. Chung and C.-Y. Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuits, vol.38, no. 2, pp. 347-351, Feb 2003.
[7]吳嘉村, “Portable Fast Locking All-Digital Phase-Lock Loop Circuit Design,” Master Thesis, National Taiwan University, Jun 2003.
[8]S. M. Rezaul Hasan, “A 5 GHz CMOS Digitally Controlled Oscillator with 3 GHz Tuning Range for PLL applications,” IEEE International Conference on Electronics, Circuits and Systems, vol 1, pp. 208-211, Dec 2003
[9]R. Saban and A. Efendovich, “A fully-digital, 2-MB/sec, CMOS data separator,” IEEE International Symposium on Circuit and Systems, vol. 3, pp. 53-56, 1994.
[10]Guang-Kaii Dehng, June-Ming Hsu, Ching-Yuan Yang, and Shen-Iuan Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1128-1136, Aug. 2000.
[11]S. J. Lee, B, Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE Journal of Solid State Circuits, vol. 32, no. 2, pp.289-291, Feb. 1997.

[12]C.H. Park and B. Kim, “A low-noise, 900MHz VCO in 0.6um CMOS,” IEEE Journal of Solid State Circuits, vol. 34, no. 5, pp.586-591, May 1999.
[13]楊怡英, “The implementation and analysis of an All Digital Phase Locked Loop,” Master Thesis, National Central University,1997
[14]曹亞嵐, “All Digital Phase Locked-Loop,” Master Thesis, National Central University,1996.
[15]劉大偉, “Design and Analysis of a Novel All Digital Phase-Locked Loop,” Master Thesis, Tamkang University, 2002.
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