臺灣博碩士論文加值系統

隨著單晶片系統的設計複雜度增高，驗證成為整個設計流程的瓶頸。現今的驗證還是依據硬體模擬。但當系統的複雜度增加，模擬時間的增高將使得模擬的效率大為降低；正確性是晶片設計者的主要目標，在特殊用途積體電路(ASIC)的設計中，功能性涵蓋率可以代表系統的正確性。如何有效減少模擬時間和增加系統的功能性涵蓋\率，成為今日積體電路設計和驗證工程師所面臨的最大難題。
為了解決上述的問題，本篇論文提出了一套SATA的匯流排功能性模組(BFM)。在行為層級方面，匯流排功能性模組制定的標準相同。藉著測試電路的行為模式，模擬時間可以被有效的控制。本文所設計的功能性模組皆是可以被控制多項參數，以及可程式化的。所以我們可應用這些模組來建構SATA的驗證環境。獨立的分層實現，簡明的設計介面和簡單的傳送/接收方法增加了這個模組的實用性。我們可以利用這個模組當成範本：藉著傳送封包給欲測試的模組，接收測試模組的回應封包來檢查欲測試模組的正確性。隨著測試檔案的增加，功能性涵蓋率可以簡單的被計算出來。論文最後提出了個驗證的環境，期望對於SATA晶片設計者，有更多的幫助。

Due to the increasing complexity of modern SoC designs, verification has become one of the bottlenecks of the entire IC design process. Current verification strategy, based on traditional hardware simulation, is not able to fulfill designer’s need efficiently because of the escalating simulation time. Functional correctness is the most fundamental requirement for all hardware design. How to reduce the simulation time and increase the functional coverage are the primary issues that designers and researchers need to solve right away.
In this thesis I provide a set of Serial ATA (SATA) Bus Function Models (BFM), congruent to SATA specification. By testing design under verification (DUV) in the behavior level, simulation time can be reduced. The BFM are configurable and programmable. We could construct all topologies of the SATA system using the BFM. Clearly layered implementation, concisely programming interface and easily command sending and receiving methodologies make SATA BFM powerful in verifying a SATA DUV. SATA BFM can become a golden model, send packets to DUV, and receive packets from DUV to check if it’s functional correctly. With the self-checked test-cases provided, functional coverage increases significantly. Finally we will provide a SATA simulation environment using SATA BFM for designers to be a reference in chip or ip design.

CHAPTER 1. Introduction 19
1.1. Concept of Bus Functional Model 19
1.2. SATA Bus Functional Models 20
1.3. TestWizard Toolkit 21
1.4. Organization of this Thesis 22
CHAPTER 2. Overview of SATA System 23
2.1. General Overview 23
2.1.1. Parallel ATA Interface 23
2.1.2. Limitations of Parallel ATA 24
2.1.3. Serial ATA Interface 24
2.1.4. Benefits of Serial ATA 24
2.1.5. Connectivity difference between Parallel ATA and Serial ATA 25
2.2. Layered Functionality 27
2.2.1. Physical Layer 27
2.2.2. Link Layer 28
2.2.3. Transport Layer 31
2.2.4. Application Layer 37
2.3. Error Handling 39
CHAPTER 3. SATA BFM Architecture 41
3.1. Overview 41
3.1.1. Compare with PCI-Xactor Implementation 41
3.1.2. SATA BFM Architecture Overview 43
3.1.3. Basic Transmit/Receive data flow of SATA BFM 43
3.2. Layered Implementation 46
3.2.1. Physical Layer 46
3.2.2. Link Layer 49
3.2.3. Transport Layer 52
3.2.4. Application Layer 54
3.2.5. Shadow Register/Device Register 56
3.3. Device Programming Interface 59
3.3.1. Error Insertion 59
3.3.2. Checklist Item Coverage 62
CHAPTER 4. Enhancement of SATA BFM 65
4.1. SATA BFM with Link Monitor 65
4.2. Purposed SATA Verification Environment 68
CHAPTER 5. Conclusion and Future works 71
5.1. Conclusion 71
5.2. Future Works 72
Reference 73

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