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[1] Y. Moon, J.Choi, K. Lee, D. K. Jeong, M. K. Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance”, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp 377-384, March 2000. [2] Y. J. Jung, S. W. Lee, D. Shim, W. Kim, C. Kim, S. I. Cho, “A dual-loop delay-locked loop using multiple voltage-controlled delay lines”, IEEE J. Solid-State Circuits, vol. 36, no. 5, pp 784-791, May 2001. [3] D. J. Foley, and M. P. Flynn, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator”, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp 417-423, March 2001. [4] M. Mota, J. Christiansen, “A high-resolution time interpolator based on a delay locked loop and an RC delay line”, IEEE J. Solid-State Circuits, vol. 34, no. 10, pp 1360-1366, Oct. 1990. [5] J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops”, IEEE J. Solid-State Circuits, vol. 31, no. 7, pp 952-957, July 1996. [6] R.B. Watson, Jr. and R. B. Iknaian, “Clock buffer chip with multiple target automatic skew compensation”, IEEE J. Solid-State Circuits, vol. 30, no. 11, pp 1267-1276, Nov. 1995. [7] S. I. Liu, J. H. Lee, and H. W. Tsao, “Low-power clock-deskew buffer for high-speed digital circuits”, IEEE J. Solid-State Circuits, vol. 34, no. 4, pp 554-558, Apr. 1999. [8] H. Sutoh, K. Yamakoshi and M. Ino, “Circuit techniques for skew-free clock distribution”, IEEE Custom Integrated Circuits Conf., pp. 163-166 1995 [9] C. Y. Yang, S. I. Liu, “A One-Wire Approach for Skew-Compensating Clock Distribution Based on Bidirectional Techniques”, IEEE J. Solid-State Circuits, vol. 36, no. 2, pp 266-272, Feb. 2001. [10] M. Galles et al. “Spider: a high-speed network interconnect”, IEEE Micro, J vol. 17, no. 1, pp. 34-39, Jan.-Feb. 1997. [11] John E. McNamara, “Technical Aspects of Data Communication”, 2nd ed., Digital Press, Bedford, MA, 1982. [12] G.. Chien and P. R. Gray, “A 900MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications”, IEEE J. Solid-State Circuits, vol. 35, no. 12, pp 1996-1999, Dec. 2000. [13] G.. Chien, “Low-noise local oscillator design techniques using DLL-based frequency multiplier for wireless applications”, Ph. D. dissertation, Univ. of California, Berkeley, 2000. [14] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp 1723-1732, Nov. 1996. [15] J. Begueret, Y. Deval, O. Mazouffre, A. Spataro, P. Fouillat, E. Benoit, J. Mendoza, “Clock generator using factorial DLL for video application”, IEEE Custom Integrated Circuits, pp 485-488, 2001. [16] MEAD Microelectronics Inc., “Lecture notes for phase-locked loops, oscillators, and frequency synthesizer”, 1998. [17] S. Kim, K. Lee, Y.Moon, D. K. Jeong, Y. Choi and H. K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL”, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp 691-700, May 1997. [18] G. K. Dehng, J. M. Hsu, C. Y. Yang and S. I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop”, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp 1128-1136, Aug. 2000. [19] M. J. Lee, W. J. Dally, J. W. Poulton, P. Chiang, S. E. Greenwood, “An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications”, VLSI Circuits, Digest of Technical Papers, 2001 Symposium on, pp.149-152, 2001. [20] W. Rhee, “Design of the high-performance CMOS charge pumps in the phase-locked loops”, ISCAS Circuits and Systems, proceedings of the 1999 IEEE International Symposium, vol. 2, pp. 545-548, 1999. [21] J. G.. Maneatis, “precise delay generation using coupled oscillators”, Ph. D. dissertation, Stanford University, June 1994. [22] P. Larsson, “A 2-1600-MHz CMOS clock recovery PLL with low-vdd capability”, IEEE J. Solid-State Circuits, vol. 34, no. 12, pp 1951-1960, Dec. 1999. [23] M. G. Johnson and E. L. Hudsin, “A variable delay line PLL for CPU-coprocessor synchronization”, IEEE J. Solid-State Circuits, vol. 23, no. 5, pp 1218-1223, Oct. 1998. [24] J. S. Lee, M. S. Keel, S. I. Lim, S. Kim, “Charge pump with perfect current matching characteristic in phase-locked loop”, Electronics Letters, vol. 36, no. 23, pp. 1907-1908, Nov. 2000. [25] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp 1723-1732, Nov. 1996 [26] M. Mota, J. Christiansen, “A four-channel self-calibrating high-resolution time to digital converters”, IEEE Electronics, Circuits and Systems, vol. 1, pp. 409-412, 1998. [27] J. J. Kim, S. B. Lee, T. S. Jung, C. H. Kim, S. I. Cho, and B. Kim, “Low-jitter mixed-mode DLL for high-speed DRAM application”, IEEE J. Solid-State Circuits, vol. 35, no. 10, pp 1430-1436, Oct. 2000. [28] X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS data recovery DLL using half-frequency clock”, IEEE J. Solid-State Circuits, vol. 37, no. 6, pp 711-715, June 2002. [29] H. H. Chang, “Design and Application of CMOS Digital/Analog Delay-Locked Loops”, Ph. D. dissertation, National Taiwan University, June 2004. [30] Lin Wu, William C., Black Jr., “A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator for Time-Interleaved Applications” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, Feb. 2001, pp. 396-397. [31] C. H. Park, O. Kim, B. Kim, “A 1.8-GHz Self-Calibrated Phase Locked Loop with Precise I/Q Matching”, IEEE J. Solid-State Circuits, vol. 36, no. 5, pp 777-783, May 2001 [32] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors”, IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, June 1989. [33] T. S. Lim, S. H. Wang, B. Kim, “A low jitter, fast locking delay locked loop using measure and control scheme”, SSMSD Mixed-signal Design, Southwest Symposium on, pp. 45-50, 2001 [34] H. H. Chang, J. W. Lin, C. Y. Yang, S. I. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002. [35] B.Kim, “High speed clock recovery in VLSI using hybrid analog/digital techniques,”Ph. D. dissertation, Univ. of California, Berkeley, Memo. UCB/ERL M90/50, June 1990. [36] A. Harjimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 790-804, June 1999. [37] T. Saeki, M. Mitsuishi, H. Iwaki, and M. Tagishi, “A 1.3-cycle Lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for clock on demand,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1581-1590, Nov. 2000. [38] National Semiconductor, LM117/LM317A/LM317 3-Terminal Adjustable Regulator Data Sheet, National Semiconductor, Inc., 1997. [39] M.-J. E. Lee, W. J. Dally, T. Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, J. Poulton, and R. Senthinathan, “Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Tecchniques,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 614-621, April 2003. [40] R. Farjad-Rad et al., “A 0.2-2GHz 12-mW multiplying DLL for low-jitter clock synthesis in highly integrated data-communication chips,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 76-77. [41] A. Waizman, “A delay line loop for frequency synthesis of de-skewed clock,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1994, pp. 298-299. [42] M.-J. E. Lee, W. J. Dally, and P. Chiang, “Low-power, area efficient, high speed I/O circuit techniques,” IEEE J. Solid-State Circuits, vol. 35, pp. 1591-1599, Nov. 2000. [43] G. Y. Wei et al., “A variable-frequency parallel I/O interface with adaptive power-supply regulation,” IEEE J. Solid-State Circuits, vol. 35, pp. 1600-1610, April 2000. [44] T. Lee et al., “A 2.5-V CMOS delay-locked loop for an 18-Mbit 500-Megabyte/s DRAM,” IEEE J. Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994. [45] S. Tam et al., “Clock generation and distribution for the first IA-64 microprocessor,” IEEE J. Solid-State Circuits, vol. 35, pp. 1545-1552, Nov. 2000. [46] S. Sidiropoulos and M. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, Nov. 1997.
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