臺灣博碩士論文加值系統

近年來由於無線通訊系統的蓬勃發展以及無線通訊市場的快速成長，射頻前端接收發器的研究如雨後春筍般成長。其中以低功耗、低成本、高整合性電路為目前無線通訊科技的主流。CMOS製程成為低價無線通訊系統的熱門製程。除此之外，單晶片整合不同系統規格亦漸為設計的主流。目前IEEE 802.11系列為無線通訊系統之主要規格，802.11a為操作在5-GHz附近的頻帶，而802.11b與802.11g則操作在2.4-GHz的頻段。

在本論文中，將以整合802.11a/b/g的頻率合成器為主要研究專題。共分成三個晶片探討：適用於IEEE 802.11a/b/g之CMOS雙頻頻率合成器、適用於IEEE 802.11a/b/g之CMOS雙迴路雙頻頻率合成器以及可適性頻寬低功耗頻率合成器。雙頻的機制是以取出偶次項諧波放大的方式來取得倍頻的訊號。第一顆雙頻的頻率合成器在2.4-GHz與5.2-GHz分別達到相位雜訊-105dBc/Hz@1MHz以及 -84dBc/Hz@1MHz。整體的功耗為39mW。以台積電點三五的製程下線。第二顆的雙迴路架構則是在合理低的雜訊敏感度下加大可調範圍並可實現27%之可調頻率範圍。並將第一顆晶片加以改良，得到在2.4-GHz與5.2-GHz分別達到相位雜訊-112dBc/Hz@1MHz以及 -102.5dBc/Hz@1MHz。整體的功耗為33.7mW。同樣以台積電點三五的製程下線。第三顆的可適性頻寬則是利用可適性地加大迴路頻寬加快鎖頻速度以及減小迴路頻寬以得到較低的雜訊信號。在模擬的1.8-V電源供應當中，整體的電路只消耗了8mW而除頻器只消耗了1mW的功耗。以台積電點一八製程下線，晶片面積為0.86mm×0.73mm2。

Recently, the explosively development of the wireless communication system and the rapidly growing market has motivated research and development of the analog transceiver front end. Low-power, low-cost and high-integration integrated circuit has become the trend of the wireless technology. Those characteristic and the progress of the sub-micron CMOS process makes CMOS process has become very attractive process to implement wireless communication systems. Besides, the integration of different system in a single chip has also become the mainstream. At present, IEEE 802.11 series are the main standards of the wireless communication, and 802.11a, 802.11b, and 802.11g are the most extensively used. 802.11a operates around 5 GHz, 802.11b and 802.11g operate at 2.4GHz.

In this thesis, dual-band frequency synthesizer for IEEE 802.11a/b/g has been chosen as the research topic. A dual-band CMOS frequency synthesizer for IEEE 802.11a/b/g, a dual-loop dual-band CMOS frequency synthesizer for IEEE 802.11a/b/g, and an adaptive bandwidth low-power frequency synthesizer are presented. The dual-band function is to generate the doubled-frequency signal by amplifying the second order harmonic of the VCO. The dual-band CMOS frequency synthesizer operates in both 2.4GHz and 5.2GHz while exhibiting a phase noise of -105dBc/Hz@1MHz in 2.4GHz and -84dBc/Hz@1MHz in 5.2GHz. It also exhibits a spur level of -35dBc. It has fabricated in TSMC 0.35-um two-poly, four-metal technology and consumes 39mW. The dual-loop architecture used in the second synthesizer is to enlarge the tuning range with reasonably low noise sensitivity. A 27% frequency tuning range is achieved and exhibits a relatively good phase noise of -112dBc/Hz@1MHz in 2.4GHz and -102.5dBc/Hz@1MHz in 5.2GHz. The spur level is -40dBc. It has also been fabricated in TSMC CMOS 0.35-um two-poly, four-metal technology and consumes 33.7mW from a 3.3V supply. Finally, the adaptive bandwidth enhances the tracking capability by extending loop bandwidth and generates a low phase noise clock signal by lowering the loop bandwidth adaptively. In simulation, it exhibits very low power consumption that the whole synthesizer consumes only 8mW and the programmable divider consumes only 1mW under 1.8V operation. The synthesizer is implemented in 0.18-μm CMOS process and the die size is 0.86mm×0.73mm2.

Chapter1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3

Chapter2 PLL fundamentals 5
2.1 General considerations 5
2.1.1 Phase noise 5
2.1.2 Reference spur 7
2.1.3 Settling time 7
2.1.4 Output frequency range 8
2.2 Building blocks 8
2.2.1 Voltage Controlled Oscillator (VCO) 9
2.2.2 Frequency divider 9
2.2.3 PFD 10
2.2.4 Charge Pump 11
2.2.5 Low pass filter (LPF) 13
2.3 System analysis 13
2.4 Noise analysis 15
2.4.1 Phase noise at input 15
2.4.2 Phase noise of VCO 16

Chapter3 A Dual-Band CMOS Frequency Synthesizer for IEEE 802.11a/b/g 19
3.1 Behavior simulation 19
3.2 Circuit implementation 20
3.2.1 Phase frequency detector (PFD) 20
3.2.2 Charge pump (CP) 21
3.2.3 Voltage Controlled Oscillator (VCO) 22
3.2.3.1 Inductor 22
3.2.3.2 Varactor 23
3.2.3.3 VCO implementation 26
3.2.3.4 Doubled-frequency architecture 31
3.2.4 Frequency divider 32
3.2.5 Loop low pass filter (LPF) 36
3.2.6 Closed loop simulation 37
3.3 Experimental results 38
3.3.1 Experimental setup 38
3.3.2 Experimental results 39
3.3.2.1 VCO measurement results 40
3.3.2.2 Divider measurement results 42
3.3.2.3 Synthesizer measurement results 42
3.4 Summary 44

Chapter4 A Dual-loop Dual-Band CMOS Frequency Synthesizer for IEEE 802.11a/b/g 45
4.1 Introduction 45
4.2 Linear analysis 47
4.3 Circuit implementation 50
4.3.1 Voltage controlled oscillator (VCO) 50
4.3.2 Charge pump(CP) 52
4.3.3 Loop low pass filter (LPF) 53
4.3.4 Closed loop simulation 53
4.4 Experimental results 55
4.4.1 VCO measurement results 56
4.4.2 Synthesizer measurement results 58
4.5 Summary 60


Chapter5 An Adaptive Bandwidth Frequency Synthesizer in 0.18μm CMOS technology 61
5.1 Introduction 61
5.2 Acquisition time improvement 62
5.2.1 Lock-time 63
5.2.2 Pull-in time 63
5.2.3 A typical second order step-response characteristic 63
5.2.4 Settling-time 64
5.2.5 Reducing Tacq 65
5.3 Circuit implementation 65
5.3.1 Adaptive bandwidth controller (VCO) 66
5.3.2 Charge pump (CP) 67
5.3.3 Frequency divider 68
5.3.4 Closed loop simulation 72
5.4 Summary 74

Chapter6 Conclusion 75
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