臺灣博碩士論文加值系統

本論文中提出考慮閘極不對稱效應於雙閘完全解離絕緣體上矽金氧半元件，當上下閘極分別是N+和P+多晶矽時的電容行為和臨界電壓模型的分析。

第一章主要是針對SOI元件做一個簡介，說明SOI元件與bulk元件比較之下有那些優點。

第二章則是探討通道長度為100奈米雙閘完全解離絕緣體上矽NMOS元件，當上下閘極分別是N+和P+多晶矽時，其獨特的電容現象。

第三章則是延續第二章的研究，但多考慮閘極不對稱效應，藉此來觀察元件內部的電容行為會發生什麼樣的改變。

第四章則是臨界電壓模型的推導和驗證，文中透過保角變換的技巧，簡化了不重疊區域內邊緣電場的分析，進而推導出更精確的臨界電壓模型，並藉由二維元件模擬軟體(MEDICI)驗證之。

This thesis reports an analysis of gate misalignment effect on capacitance behavior and threshold voltage of double-gate (DG) fully-depleted (FD) silicon on insulator (SOI) NMOS device with N+/P+ poly Top/Bottom gate.

In chapter 1, we make an introduction for SOI device and describe its goods compared with the bulk one.

In chapter 2, we discuss the unique capacitance phenomenon of a 100nm DG FD SOI NMOS device with the N+/P+ poly top/bottom gate.

In chapter 3, we continue the research in chapter 2. Besides, we consider the gate misalignment effect on capacitance behavior and observe the change in it.

In chapter 4, we describe the derivation and verification of threshold voltage of DG FD SOI NMOS device with N+/P+ poly Top/Bottom gate. By using the conformal mapping transformation approach, a model considering the fringing electric field effect in the non-gate overlap region of DG FD SOI NMOS device has been derived to provide an accurate prediction of threshold voltage behavior as verified by the 2D simulation results.

1 導論 1
1-1 為什麼是SOI元件 1
1-2 部份解離 vs. 完全解離 1
1-3 SOI MOS元件 3
1-4 DG SOI MOS 元件 4
1-5 DG FD SOI MOS元件 4
1-6 本篇論文的目標 5

2 通道長度100奈米雙閘完全解離絕緣體上矽NMOS元件，當上下閘極分別是N+
和P+多晶矽時，其獨特的電容現象 6
2-1 簡介 6
2-2 電容現象 6
2-3 電容行為的分析 9
2-4 討論 14
2-5 結論 17

3 通道長度100奈米雙閘完全解離絕緣體上矽NMOS元件，當上下閘極分別是N+
和P+多晶矽時，其閘極不對稱效應與電容現象的相關性 18
3-1 簡介 18
3-2 閘極不對稱效應與電容行為的關係 18
3-3 電容行為的分析 21
3-4 討論 26
3-5 結論 30

4 考慮閘極不對稱效應於雙閘完全解離緣體上矽金氧半元件，當上下閘極分別為N+
和P+多晶矽時的臨界電壓模型 31
4-1 簡介 31
4-2 模型推導 31
4-2-1 閘極重疊區域 (I) 33
4-2-2 閘極不重疊區域 (II) 34
4-2-3 邊界條件 38
4-2-4 臨界電壓 40
4-2-5 不考慮邊緣電場效應的結果 42
4-2-6 不考慮邊緣電場效應和閘極偏移效應的結果 43
4-3 結果與討論 44
4-4 結論 51
5 總結 52

參考文獻 53

第1章
[1] J. B. Kuo,”數位 IC”,全華, 2004.
[2] J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits. New York: Wiley, 2001.

第2章
[1] J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits. New York: Wiley, 2001.
[2] A. Vandooren, S. Cristoloveanu, and J. P. Colinge, “The Dynamic Conductance and Transconductance in Double-Gate (Gate-All-Around) SOI Devices,” SOI Conf. Proc., pp. 116-117, 2000.
[3] D. Hisamoto, “FD/DG-SOI MOSFET-A Variable Approach to Overcoming the Device Scaling Limit,” IEDM Dig., 2001.
[4] K. Suzuki and T. Sugi, “Analytic Models for n+/p+ Double-Gate SOI MOSFET’s,” IEEE Trans. Electron Devices, pp. 1940-1945, 1995.

第3章
[1] J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits. New York: Wiley, 2001.
[2] A.Vandooren, S. Cristoloveanu, and J. P. Colinge, “The Dynamic Conductance and Transconductance in Double-Gate (Gate-All-Around) SOI Devices,” SOI Conf. Proc., pp. 116-117, 2000.
[3] D.Hisamoto, “FD/DG-SOI MOSFET-A Variable Approach to Overcoming the Device Scaling Limit,” IEDM Dig. 2001.
[4] K. Suzuki and T. Sugii, “Analytic Models for n+/p+ Double-Gate SOI MOSFET’s,” IEEE Trans. Electron Devices, pp.1940-1945, 1995.
[5] C. P. Yang, C. H. Hsu, and J. B. Kuo, “Unique Capacitance Phenomenon of a 100nm Double-Gate FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate, ” ICSICT Proc., 2004.
[6] Elvis C. Sun and James B. Kuo, Fellow, IEEE, “A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI nMOS Devices Considering Fringing Electrical Field Effects.”, IEEE Trans. Electron Devices, vol. 51, pp. 587-596, April 2004.

第4章
[1] J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits. New York: Wiley, 2001.
[2] D.Hisamoto, “FD/DG-SOI MOSFET-A Variable Approach to Overcoming the Device Scaling Limit,” IEDM Dig. 2001.
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[5] S. Chen and J. Kuo, ”Deep submicrometer double-gate fully-depleted SOI PMOS devices: A Concise short-channel effect threshold voltage model using a quasi-2-D approach,” IEEE Trans. Electron Devices, vol. 44, pp. 1387-1393, Sept. 1996.
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[7] Widiez, J.; Dauge, F.; Vinet, M.; Poiroux, T.; Previtali, B.; Mouis, M.; Deleonibus, S. “Experimental gate misalignment analysis on double gate SOI MOSFETs” SOI Conf. Proc., pp. 185-186, 2004.
[8] Chunshan Yin; Chan, P.C.H.; Chan, V.W.C., “Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis”, IEEE Electron Device Letter, vol. 24, pp. 658-660, 2003.
[9] Chunshan Yin; Chan, P.C.H., “Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs” IEEE Trans. Electron Devices, pp.85-90, 2005.
[10] Jian Shen; Tsz Yin Man; Mansun Chan, “2D analysis of bottom gate misalignment and process tolerant for sub-100 nm symmetric double-gate MOSFETs”, Electron Devices and Solid-State Circuits, IEEE Conf., pp. 201-204, 2003.
[11] J. B. Kuo, E. C. Sun, M. T. Lin, “Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD)” in EDMO, pp. 83-86, Nov. 2003.
[12] Elvis C. Sun and James B. Kuo, Fellow, IEEE, “A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI nMOS Devices Considering Fringing Electrical Field Effects.”, IEEE Trans. Electron Devices, vol. 51, pp. 587-596, April 2004.
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