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研究生:廖彥鈞
研究生(外文):Yen-Chun Liao
論文名稱:Gigabit等級分碼多工式乙太被動式光纖網路平台於場式可程式化閘陣列上之實作
論文名稱(外文):CDMA Gigabit-Ethernet Passive Optical Network Design and Implementation in FPGA
指導教授:吳靜雄
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:86
中文關鍵詞:被動式乙太光纖網路光分碼多工完美相差碼光線路終端光網路單元
外文關鍵詞:EPONOCDMAPDCOLTONU
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隨著網際網路的快速發展,用戶對頻寬的需求量也大幅增加。研究顯示,自1990年開始網路上資料的傳輸量正以超過百分之百的速度在快速增加(在1995及1996年增加量甚至超過1000%)。骨幹網路在頻寬使用率上,由於光通訊原件科技的大幅進步以及DWDM應用逐漸成熟的影響下,一直都是處於非飽和的狀態上,但是現今頻寬供給的量似乎並沒有跟著頻寬需求一起大幅成長,最主要的瓶頸還是出在最後一哩(last mile)的接取網路上。為了要解決頻寬不足的瓶頸,在最後一哩必須引進光纖設備,考量到乙太網路在區域網路的廣泛佔有率以及容易擴充與管理的特性,被動式乙太光纖網路結合了低成本的乙太網路設備與低成本的光纖網路架構,應該是下一代存取網路的最佳方案之一。

在本篇論文中,我們設計並實作了一個全新同步演算法的被動式乙太光纖網路。在我們提出的系統裡上行端採用同步光分碼多工存取方式而非常見之分時多工存取來避免碰撞。我們採用完美相差碼來作為同步分碼多工之展頻碼。我們實作上架設了包含一個光線路終端(Optical Line Terminal)與兩個光網路單元(Optical Network Unit)的被動式乙太光纖網路雛形系統。同時我們也驗證了所提出的同步方式並且可以達到125微微秒以內的誤差。我們利用場式可程式化閘陣列(FPGA)來實作光線路終端與光網路單元之電路。在本文中,我們詳細描述所有系統模組的設計流程與操作原理並包含整體系統的完整模擬。最後成功的完成20公里上傳十億兩千五百萬位元下傳壹百億位元乙太被動式光網路。
In recent years the bandwidth of backbone network has experienced substantial growth, but little has changed in the access networks. To solve bandwidth bottlenecks of access network, optical fibers are necessary in the last mile. Considering that Ethernet, which is low cost and easy to installation and management, has conquered the ground in local area networks (LANs), Ethernet passive optical network (EPON) may be the best solution for the broadband access. EPON combines the low cost Ethernet equipment and low cost fiber infrastructure, which is the promising candidate of next generation of last mile.

In this thesis, we design and implement an EPON with a new upstream scheme for fiber-optic code division multiple access (CDMA) systems. In the proposed system, we adopt Synchronous Optical CDMA scheme in the upstream traffic rather than the conventional scheme of time division multiple access (TDMA). Perfect difference codes are adopted as our synchronous spreading codes. An EPON system which includes one optical line terminal (OLT) and two optical network units (ONUs) is experimentally implemented. System synchronization is realized and the synchronization error less than 125ps is achieved. The OLT/ONU circuits are implemented by a Field-Programmed-Gate-Array. We describe the design flow and operation principle of each module, and complete the whole simulation of the system. Finally, we demonstrate a 20 km EPON system with downlink 10Gbps and uplink 1.25Gcps transmission rates successfully.
Contents

中文摘要     i

Contents ii

Abstract v

CHAPTER 1 INTRODUCTION 1
1.1 BASIC CONCEPT OF PON 1
1.2 BASIC CONCEPT OF EPON 3
1.3 ORGANIZATION OF THE THESIS 5

CHAPTER 2 ARCHITECTURE OF GIGABIT-CDMA EPON 7
2.1 OVERVIEW 7
2.2 PERFECT DIFFERENCE CODES 7
2.3 SYSTEM ARCHITECTURE 11
2.4 SYNCHRONIZATION 15

CHAPTER 3 DESCRIPTION OF OLT FOR CIRCUIT DESIGN 23
3.1 OVERVIEW 23
3.2 DESIGN OF OLT_CTRL UNIT 24
3.2.1 Function Description 24
3.2.2 State Diagram 25
3.2.3 Sub-module and simulation waveform 27
3.2.4 I/O Definition 31
3.3 DESIGN OF ADC RECEIVER 32
3.3.1 Function Description 32
3.3.2 Sub-module and simulation waveform 32
3.3.3 I/O Definition 36
3.4 DESIGN OF 10GBE PCS TX PART 37
3.4.1 Function Description 37
3.4.2 Sub-module and simulation waveform 38
3.4.3 I/O Definition 42
3.5 THE REST CIRCUIT DESIGN OF OLT 43
3.5.1 tx_clocks 43
3.5.2 Packet generator & packet receiver 43

CHAPTER 4 DESCRIPTION OF ONU FOR CIRCUIT DESIGN 45
4.1 OVERVIEW 45
4.2 DESIGN OF ONU_CTRL UNIT 46
4.2.1 Function Description 46
4.2.2 State Diagram 46
4.2.3 Sub-module and simulation waveform 48
4.2.4 I/O definition 51
4.3 DESIGN OF ONU_TX UNIT 52
4.3.1 Function Description 52
4.3.2 State Diagram 52
4.3.3 Sub-module and simulation waveform 54
4.3.4 I/O definition 58
4.4 DESIGN OF 10GBE PCS RX PART 59
4.4.1 Function Description 59
4.4.2 Sub-module and simulation waveform 59
4.4.3 I/O Definition 63
4.5 THE REST CIRCUIT DESIGN OF ONU 64
4.5.1 rx_clocks 64
4.5.2 Rocket I/O 64

CHAPTER 5 FPGA IMPLEMENTATION AND EXPERIMENT RESULTS 67
5.1 FPGA ARCHITECTURE 67
5.2 FPGA DESIGN FLOW 69
5.3 EXPERIMENT ENVIRONMENT AND RESULTS 72

CHAPTER 6 CONCLUSIONS 83

REFERENCE: 85
[1] R. Ramaswami and K. N. Sivarajan, Optical networks: a practical perspective, Morgan Kaufmann Publishers, Inc., 1998.

[2] Kramer, G. and Pesavento, G.., "Ethernet passive optical network (EPON): building a next-generation optical access network," IEEE Communications Magazine, Volume: 40 Issue: 2, Feb 2002.

[3] Chi-Shun Weng and Jingshown Wu, “Perfect difference codes for synchronous fiber-optic CDMA communication systems,” J. Lightwave Technol., vol. 19, no.2, pp. 186-194, Feb. 2001.

[4] J. Singer, “A theorem in finite projective geometry and some applications to number theory,” Trans. Amer. Math. Soc., vol. 43, pp. 377-385, 1938

[5] Po-Chiun Huang, “Design and Implementation of an Ethernet Passive Optical Network Using Perfect Difference Codes,” M.S. Thesis 2003, Graduate Institute of Communication Engineering, National Taiwan University.

[6] Shin-Kuan Chang, “Design and Implementation of Code Division Multiple Access Netwrok Based on EPON Technology,” M.S. Thesis 2003, Graduate Institute of Communication Engineering, National Taiwan University.

[7] “IEEE Standard for Information technology- Telecommunications and information exchange between systems- Local and metropolitan area networks- Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation,” IEEE standard 802.3ae, 2002.

[8] 300PINMSA Group, “Reference Document for 300pin 10Gb Transponder”, Aug, 2002.

[9] “http://www.national.com/ds.cgi/DC/ADC08D1000.pdf”, ADC08D1000 datasheet , National Semiconductor

[10] Xilinx Corporation, “Virtex-II Pro Application Notes,” 2004.

[11] Xilinx Corporation, “Virtex-Π ProTM Platform FPGA User Guide,” April, 2004.

[12] Xilinx Corporation, “Virtex-II ProTM Platform FPGAs: Complete Data Sheet,” April, 2004.

[13] Xilinx Corporation, “RocketIOTM Transceiver User Guide,” May 20, 2004.

[14] “Verilog Training Manual,” National Science Council CIC, July 2001.

[15] Chia-Chu Ho, “Design and Implementation of a 10G Ethernet Passive Optical Network system with upstream traffic multiplexed by Code Division Multiple Access”, M.S. Thesis 2005, Graduate Institute of Communication Engineering, National Taiwan University.
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