臺灣博碩士論文加值系統

本論文目的在於研究使用商用標準金氧半場效電晶體積體電路製程來設計具有更佳特性之低雜訊放大器。論文中使用了兩種改善雜訊特性的方法設計金氧半場效電晶體之低雜訊放大器。
第一個用來改善低雜訊放大器雜訊特性的方法是選擇電晶體大小以達到雜訊最佳化的目的。本論文所展現的方法由於是將晶片上電感的寄生電阻直接納入低雜訊的設計過程，可以比一般傳統的方法得到更合適的電晶體。此電路在10 GHz的頻帶中，量測結果顯示11.25 dB的增益，以及低於3 dB的雜訊指數。
第二個用來改善低雜訊放大器雜訊特性的方法是在串極串基架構(cascode)中間以並聯共振的方式，進一步降低整個放大器的雜訊。此方法將上一個電路的雜訊進一步降低為2.5 dB(改善了約0.5 dB)。

The purpose of this thesis is to develop low noise amplifiers employing commercial standard CMOS processes to achieve better noise performance. Two methods to improve the noise characteristics were used to design LNAs.
The first approach for improving noise characteristics of the LNA is using the device-size selection to optimize the noise performance. By incorporating the series resistances of the on-chip inductors into the noise optimization procedure, the optimum device size can be selected more appropriately. The 10 GHz LNA has a measured gain 11.25 dB with the noise figure below 3 dB.
The second approach for improving noise characteristics of the LNA is using the parallel-resonant technique between the two stages of the cascode LNA, the LNA achieved measured noise figure of 2.5 dB, which is about 0.5 dB noise figure improvement over the first circuit.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Literature Survey 2
1.3 Contributions 3
1.4 Chapter Outlines 4
CHAPTER 2 INTRODUCTION OF LOW NOISE AMPLIFIERS 5
2.1 Operation of Low Noise Amplifiers 5
2.2 Methods to Improve the Noise Characteristics of Low Noise Amplifiers 20
CHAPTER 3 LOW NOISE AMPLIFIERS USING AN IMPROVED NOISE-OPTIMIZATION METHOD 28
3.1 The Conventional Noise-Optimization Method 30
3.2 The Improved Noise-Optimization Method 33
3.3 LNA Design 35
3.4 LNA Measurements 40
3.5 Summary 44
CHAPTER 4 LOW NOISE AMPLIFIERS USING PARALLEL-RESONANT TECHNIQUE 45
4.1 Motivation 46
4.2 Design Principle 49
4.3 LNA Design and Measurements 57
4.4 Summary 64
CHAPTER 5 CONCLUSIONS 65
REFERENCES 68

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