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研究生:黃致文
研究生(外文):C.W. Huang
論文名稱:絕緣體上矽金半場效電晶體其三維解析模型分析及研究
論文名稱(外文):Three-Dimensional Analytical Models for SOI-MESFET's
指導教授:Dr. 江德光
指導教授(外文):T.K. Chiang
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:41
外文關鍵詞:SOI-MESFET''snarrow-width effectPoisson''s equation
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隨著數位積體電路面積的增加, 絕緣層上的矽金半場效電晶體(SOI-MESFET)其次臨界(subthreshold)傳導現象更顯的重要。 加上金半場效電晶體可以滿足超大型積體電路(ULSI)的製程技術,因此也逐漸備受重視。 然而一般的文獻卻鮮少有關三維(three-dimensional)的矽金半場效電晶體的帕森方程式(Poisson’s equation)的推導。 當元件面積縮小到次微米(submicrometer)的時候,短通道效應(short-channel effect)和窄通道效應(narrow-width effect)會顯的特別明顯。 然而想要探討短通道效應,至少必須是二維的帕森方程式。 而在此處的三維帕森方程式是利用疊加法(superposition principle)來推導分析。 三維的帕森方程式須經過相當複雜的演算,那是由一維的帕森方程式和二維的拉普拉斯方程式(Laplace equation)以及三維的拉普拉斯方程式所組成。 推導過程有一些相當繁複的傅立葉級數(Fourier series),經由這些式子來求出最小的通道底部電位(minimum bottom potential)。 然後再更進一步求出臨界電壓(threshold voltage)。
而在這裡,藉由數學式的推導結果來進行數值分析(numerical analysis), 並利用三維的模擬軟體DAVINCI來模擬出三維的矽金半場效電晶體的各種次臨界現象, 並將數值分析的結果和DAVINCI模擬的結果互相比較。 然而會影響臨界電壓效能的參數有很多種,在這裡我們將通道長度,寬度還有通道的參雜密度(channel doping density)改變,來觀察它們對臨界電壓的影響。 並針對小體積元件,大體積元件, 短通道元件或是窄通道元件來加以模擬比較。 觀察窄通道元件對“汲極電壓引發通道位能障壁降低效應”(drain-induced barrier lowering effect, DIBL)的影響。 另外, 當我們加一些小偏壓在汲極電壓時,汲極電壓引發通道位能障壁降低的效應反而更嚴重。
Recent years, MESFET’s has been considerable due to it can satisfy the ULSI technology. However, there are very few models for three-dimensional SOI-MESFET’s device. In this case, three-dimensional SOI-MESFET model explores the short-channel effect and narrow-width effect. From three-dimensional Poisson’s equation has been developing by superposition principle. There is a numbers of complicated Fourier series are derived.
The minimum bottom potential can be obtained by the three-dimensional Poisson’s equation. Furthermore, the threshold voltage also can be achieved from the bottom potential. Numerical analysis compare with the DAVINCI simulation result are proposed. The parameters of device structure, like channel length, channel width, and silicon film thickness can affect the threshold voltage shift. Besides, the increased drain-source bias will initiate the DIBL (drain-induced barrier lowering) effect. The DIBL effect for the short-channel device may be demonstrated by the bottom potential.
摘  要 I
ABSTRACT II
ACKNOWLEDGEMENTS III
CHAPTER 1 ABSTRACT (CHINESE) IV
CHAPTER 2 ABSTRACT (CHINESE) V
CHAPTER 3 ABSTRACT (CHINESE) VI
CHAPTER 4 ABSTRACT (CHINESE) VII
CHAPTER 5 ABSTRACT (CHINESE) VIII
CONTENTS IX
LIST OF FIGURES XI
CHAPTER 1 INTRODUCTION 1
1.1 MESFET’S REVIEW 1
1.2 DISSERTATION ORGANIZATION 3
CHAPTER 2 DAVINCI OVERVIEW AND DEVICE CONFIGURATIONS 4
2.1 DAVINCI OVERVIEW 4
2.2 DEVICE CONFIGURATIONS 4
CHAPTER 3 METHOD OF 3-D ANALYTICAL MODELING 10
3.1 MOTIVATIONS 10
3.2 THE ANALYSIS OF THREE-DIMENSIONAL POTENTIAL 10
3.3 MINIMUM BOTTOM POTENTIAL 17
3.4 SMALL-GEOMETRY THRESHOLD VOLTAGE MODEL 20
3.4.1 Narrow-width effect and Short-channel effect 21
CHAPTER 4 3-D SIMULATION RESULTS AND DISCUSSIONS FOR SOI-MESFET’S 23
4.1 MOTIVATIONS 23
4.2 SMALL-GEOMETRY THRESHOLD VOLTAGE SIMULATION 23
4.3 SHORT-CHANNEL EFFECTS AFFECT THE THRESHOLD VOLTAGE 25
4.4 NARROW-WIDTH EFFECTS AFFECT THE THRESHOLD VOLTAGE 31
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 35
5.1 CONCLUSIONS 35
5.2 FUTURE WORKS 35
PUBLICATIONS LIST 36
REFERENCES 37
[1] J. J. Liou, A. Ortiz-Conde, and F. Garcia-Sanchez, “Analysis and Design of MOSFET’s Modeling, Simulation, and Parameter Extraction,” Kluwer Academic Publishers.
[2] J. S. Yuan. and J. J. Liou., “Semiconductor Device Physics and Simulation,” Plenum Publishing Corporation (May 1, 1998).
[3] J.J. Liou, Frank Schwierz, “Modern Microwave Transistors: Theory, Design, and Performance,” Wiley Interscience; (2003).
[4] T. K. Chiang, Y. H. Wang, and M.P. Houng, “Modeling of threshold voltage and subthreshold swing of short-channel SOI MESFET’s,” Solid-State Electron., vol. 43, pp. 123-129, 1999.
[5] J. D. Marshell and J. D. Meindl, “A sub- and near-threshold current model for silicon MESFET’s,” IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 388-390, March 1988.
[6] A. Georagkilas, G. Halkias, A. Christou, C. Papavassiliou, G. Perantinus, G. Konstantinidis, and P. Panayotatos, “Microwave performance of GaAs-on-Si MESFET’s with Si buffer layers,” IEEE Trans. Electron Devices, vol. 40, no. 3, pp. 507-512, March 1993.
[7] U. Magnusson, J. Tiren, A. Soderbarg, M. Rosling, O. Grelsson, H. Bleichner, J. O. Nylander, and S. Berg, “Bulk silicon technology for complementary MESFET’s,” IEEE Electron Device Letters, vol. 25, no. 9, pp. 565-566, April 1989.
[8] Nishihori, K.; Kitaura, Y.; Hirose, M.; Mihara, M.; Nagaoka, M.; Uchitomi, N.; “A self-aligned gate GaAs MESFET with p-pocket layers for high-efficiency linear power amplifiers,” IEEE Trans., Electron Devices, vol. 45, no. 7, pp. 1385-1392, July 1998.
[9] P. A. Tove, K. Bohlin, F. Masszi, H. Norde, J. Nylander, J. Tiren, and U. Magnusson, “Complementary Si-MESFET concept using silicon-on-sapphire technology,” IEEE Electron Device Letters, vol. 9, no. 1, pp. 47-49, Jan. 1988.
[10] J. G. Cao, “A simplified 2-D analytic model for the threshold-voltage of fully depleted short gate-length Si-SOI MESFET’s,” IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1314-1315, Aug. 1996.
[11] S. M. Sze, “Physics of Semiconductor Devices,” 2nd. New York: Wiley, 1983.
[12] S. P. Chin and C. Y. Wu, “A new two-dimensional model for the potential distribution of short gate-length MESFET’s and its applications,” IEEE Trans. Electron Devices, vol. 39, no. 8, pp. 1928-1937, Aug. 1992.
[13] C.S. Hou and C.Y. Wu, “A 2-D Analytic model for the threshold voltage of fully depleted short gate-length Si-SOI MESFET’s ,”IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2156-2162, Dec. 1995.
[14] MacWilliams, K. P. and Plummer, J. D., “Device physics and technology of complementary silicon MESFET’s for VLSI applications,” IEEE Trans. Electron Device, vol. 38, no. 12, pp. 2619-2631, Dec. 1991.
[15] Prashant Pandey, B. B. Pal, and S. Jit, “A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFET’s,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 246-254, Feb. 2004.
[16] K. N. Ratnakumar and J. D. Meindl, “Short-channel MOST threshold voltage model,” IEEE Journal of Solid-State Circuits, vol. 17, no. 5, pp. 937-948, Oct. 1982.
[17] Peatman W. C. B., Hurt M. J., Hyunchang Park, Ytterdal T., Tsai R. and Shur M. S., “Narrow channel 2-D MESFET for low power electronics,” IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1569-1573, Sept. 1995.
[18] Jinman Yang, Spann J., Anderson R. and Thornton T., “High-frequency performance of subthreshold SOI MESFET’s,” IEEE Electron Device Letters, vol. 25, no. 9, pp. 652-654, Sept. 2004.
[19] Chian-Sern Chang, Ding-Yuan S. Day, Simon Chan, “An analytical two-dimensional simulation for the GaAs MESFET drain-induced barrier lowering: A short-channel effect,” IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1182-1186, May 1990.
[20] E. Donkor, F. C. Jain, “An analytical two-dimensional perturbation method to model submicron GaAs MESFET’s,” IEEE Trans. Microwave Theory And Techniques, vol. 37, no. 9, pp. 1484-1487, Sept. 1989.
[21] Shirokov M.S., Leoni R.E.lll, Bao J., Hwang J.C. M., “A transient SPICE model for digitally modulated RF characteristics of ion-implanted GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. 47, no. 8, pp. 1680-1681, Aug. 2000.
[22] J. D. Marshall and J. D. Meindl, “An analytical two-dimensional model for silicon MESFET’s,” IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 373-383, March 1988.
[23] K. N. Ratnakumar and J. D. Meindl, “Short-channel MOST threshold voltage model,” IEEE Solid-State Circuits, vol. 17, no. 5, pp. 937-948, Oct. 1982.
[24] Mohammad S., Patil M.B., Morkoc H., “Heavy doping for improved short-channel operation of GaAs MESFET’s,” IEEE Electronics Letters, vol. 25, no. 5, pp. 331-332, March 1989.
[25] R. R. Troutman, “VLSI limitation from drain induced barrier lowering,” IEEE Solid-State Circuits, vol. 14, no. 2, pp. 383-391, Apr. 1979.
[26] Agrawal B., De V. K. and Meinal J. D., “Three-dimensional analytical subthreshold models for bulk MOSFET’s,” IEEE Trans. Electron Devices, vol. 42, no. 12, pp. 2170-2180, Dec. 1995.
[27] De V. K. and Meindl J. D., “Three-region analytical models for MESFET’s in low-voltage digital circuits,” IEEE Journal of Solid-State Circuit, vol. 26, no. 6, pp. 850-858, June 1991.
[28] R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits,” IEEE Journal of Solid-State Circuits, vol. 7, no. 2, pp. 146-153, July 1972.
[29] J. Conger, “Subthreshold current in GaAs MESFET’s,” IEEE Electron Device Letters, vol. 9, no. 3, pp. 128-129, Sept. 1988.
[30] Nummila K., Ketterson A. A., Caracci S., Kolodzey J., Adesida I., “Short-channel effects in sub-100 nm GaAs MESFET’s,” IEEE Electronics Letters, vol. 27, no. 17, pp. 1519-1521, Aug. 1991.
[31] Assaderaghi F., Chen J., Solomon R., Chian T-Y., Ko P.K., Hu C., “Transient behavior of subthreshold characteristics of fully depleted SOI MOSFET’s,” IEEE Electron Device Letters, vol. 12, no. 10, Oct. 1991.
[32] Frank D. J., Dennard R. H., Nowak E., Solomon P. M., Taur Y. and Hon-Sum Philip Wong, “Device scaling limits of Si MOSFET’s and their application dependencies,” Proceedings of the IEEE, vol. 89, no. 3, pp. 259-288, March 2001.
[33] Webster D., Darvishzadeh M. and Haigh D., “Total charge capacitor model for short-channel MESFET’s ,” IEEE Microwave and Wireless Components Letters, vol. 6, no. 10, pp. 351-353, Oct. 1996.
[34] Hartgring C. D., Rosario B. A. and Pickett J. M., “Silicon MESFET digital circuit techniques,” IEEE Journal of Solid-State Circuits, vol. 16, no. 5, pp.578-584, Oct. 1981.
[35] K. P. MacWiliams and J. D. Plummer, “Device physics and technology of complementary silicon MESFET’s for VLSI applications,” IEEE Trans. Electron Devices, vol. 38, no. 12, pp. 2619-2631, Dec. 1991.
[36] Houston T. W. and Darley H. M., “Comments on Silicon MESFET digital circuit technology,” IEEE Journal of Solid-State Circuit, vol. 18, no. 2, pp. 229-230, Apr. 1983.
[37] J. Nulman, J. V. Faricelli, J. P. Krusius, and J. Frey, “Fabrication and analysis of 1/2 um silicon logic MESFET’s,” IEEE Trans. Electron Devices, vol. 30, no. 10, pp. 1395-1401, Oct. 1983.
[38] T. Wada and J. Frey, “Physical basis of short-channel MESFET operation,” IEEE Journal of Solid-State Circuits, vol. 14, no. 2, pp. 398-412, Apr. 1979.
[39] Horio, K. and Satoh, K, “Two-dimensional analysis of substrate-related kink phenomena in GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2256-2261, Dec. 1994.
[40] Joachim H.O., Yamaguchi Y., Ishikawa K., Inoue Y., Nishimura T., “Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFET’s down to 0.1um gate length,” IEEE Tran. Electron Devices, vol. 40, no. 10, pp. 1812-1817, Oct. 1993.
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