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研究生:施力嘉
研究生(外文):Lie-Chia Shie
論文名稱:藉由調變測試程式參數以縮短快閃記憶體測試時間之研究
論文名稱(外文):Studies on Tuning Parameters of Test Program to Save Flash Memory Test
指導教授:黃恆盛黃恆盛引用關係
指導教授(外文):Heng-Sheng Huang
口試委員:王木俊陳雙源
口試委員(外文):Mu-Chun WangShuang-Yuan Chen
口試日期:2000-07-21
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:機電整合研究所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:60
中文關鍵詞:記憶體測試NOR型快閃記憶體NAND型快閃記憶體測試程式
外文關鍵詞:Memory TestingNOR-type FlashNAND-type FlashTesting Program
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快閃記憶體容量隨著人們的需求快速增加,對測試產業而言,帶來的影響是增長快閃記憶體的測試時間,造成測試成本上升。本論文藉由調變測試程式參數,探討減少測試時間的各種可能性與原因。研究之步驟是,首先選定IC電源電壓與測試頻率作為調變的參數,然後分別對NOR型與NAND型的快閃記憶體作實驗及分析,最後得到各參數與測試時間的關係,整理出對開發測試程式人員的建議。
就NOR型的快閃記憶體測試來說,本研究發現,在相同測試條件下,隨著IC電源電壓升高可以減少測試時間,因為電壓越高則寫入與擦拭的動作會越快完成,且測試項目中最為費時的就是寫入時間;提高測試頻率也可以減少測試時間,因為較高的頻率加快測試指令下達的速度與資料傳輸的時間,對於減少讀取與寫入的時間有極大的幫助。就NAND型的快閃記憶體測試來說,IC電源電壓的變化對於測試時間的影響變得不明顯,而測試頻率的改變對於測試時間卻有極大的變化,由於 NAND型的快閃記憶體讀取速度緩慢,讀取時間相對於整體測試時間的比例增加,因此高的測試頻率能更有效的降低測試時間。
經由觀察及分析可得如下結論,提高測試頻率是降低測試時間最有效的方法,而提高IC電源電壓適用於低記憶容量NOR型的快閃記憶體,面對未來的高記憶容量的需求,高測試頻率的突破將是主要的重點。
The capacity of flash memory increases speedily due to people''s requirement. However, to testing business, test time is becoming longer and test cost is becoming higher. The topic in this paper is to discuss the different kinds of possibilities and the reasons for reducing test time by tuning the parameters of test program. In the beginning of the research, IC supply voltage and testing frequency are chosen to be the parameters for varying. And then, flash memories of the NOR-type and NAND-type are tested and analyzed. Finally, the relationships of two parameters with test time are obtained. Based on the results, suggestions are provided to assist engineers in this field to select best parameters for saving test time of flash memories.
To NOR-type flash memory, the research finds that under the same testing condition, the test time can be decreased owing to the increase of IC voltage supply. It''s reasonable because higher voltage leads to faster for most of the time consumed in programming and erasing. Additionally, the testing time can be shorter by promoting the testing frequency because higher frequency accelerates the speed of giving the testing orders and receiving tested data.
As far as NAND-type flash memory is concerned, the research finds that the variety of IC voltage supply only has little influence on the test time, but the alteration of test frequency is quite helpful. That is because the reading speed of NAND-type flash memory is slow, thus the reading time are dominant in the whole test time. Therefore, high test frequency can effectively reduce test time.
Through painstaking observation and analysis, the following conclusion can be made: raising the test frequency is the most efficient method to lessen test time. In addition, increasing the IC voltage supply is only suitable for NOR-type flash memory that owns small memory capacity. To face the demand for high memory capacity in the future, the main strategy should be to make a breakthrough of using high test frequency.
Abstract(Chinese)……………………………………………………………….. i
Abstract(English)……………………………………………………………….. ii
Acknowledgement…………………………………………………………………..iv
Contents…………………………………………………………………………….. v
List of Tables……………………………………………………………………….vii
List of Figures……………………………………………………………………..viii
Chapter1 Introduction……………………..…………………………….…………..1
1.1 Research Background and Motivation………………………………………1
1.2 Thesis Organization…………………………………………………………2
Chapter 2 Flash Memory Overview………………………………………………..3
2.1 Introduction Flash Memory…………………………………………………3
2.2 Flash Memory Structure and Capacitance Model…...………………………5
2.3 Carrier Transport Classification……………………………………………..8
2.3.1 Channel Hot carrier injection…………………………………………..9
2.3.2 Drain Avalanche Hot Carrier Injection………………………………..11
2.3.3 Fowler-Nordheim tunneling…………………………………………..12
2.4 Flash Memory Operation and Mechanisms……………………………….13
2.4.1 Reading of Flash Memory…………………………………………….13
2.4.2 Programming of Flash Memory………………………………………15
2.4.3 Erasing of Flash Memory……………………………………………..18
2.5 Array Architecture…………………………………………………………20
2.5.1 NOR-type Flash Memory……………………………………………..20
2.5.2 NAND-type Flash Memory…………………………………………...21
2.6 Flash Memory Device……………………………………………………..22
2.7 Flash Memory Application………………………………………………...24
Chapter 3 Test Technology Overview……………………………………………...26
3.1 Conceptual Test Flow……………………………………………………..26
3.2 Test Program………………………………………………………………28
3.2.1 DC Testing……………………………………………………………29
3.2.2 Function Testing……………………………………………………...30
3.2.3 Special Test mode…………………………………………………….34
3.3 Test Cost......................................................................................................35
Chapter 4 Experimental Results and Discussion………………………………….36
4.1 Experiment System Setup………………………………………………...36
4.2 Information of Device…………………………………………………….37
4.3 Experiment Parameter Setting………………………………….................38
4.4 Experimental program Test……………………………………………….40
4.4.1 Test with Different Supply Voltage…………………........................41
4.4.2 Test with Different Test Frequency…………………........................43
4.4.3 Experiment Analysis by Operations…...............................................45
4.4.3.1 Active Current with Different Supply Voltage.........................45
4.4.3.2 Programming Speed with Different Conditions.......................46
4.4.3.3 Erasing Speed with Different Conditions.................................48
4.4.3.4 Reading Speed with Different Conditions................................50
4.4.4 Summary of Experiment....................................................................53
4.5 Process Program Test for Result and Verify................................................53
Chapter 5 Conclusion and Further Research……………………………………..57
5.1 Conclusion………………………………………………………………...57
5.2 Further Research………………………………….....................................58
Reference………………………………………………………………………........59
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[2] M. She, Semiconductor Flash Memory Scaling, Ph.D., University of California, Berkeley, 2003.
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[4] P. Cappelletti et al, Flash Memories, Boston, 1999.pp.16-22,137-142.
[5] T. Kitamura et al,”A low voltage operating flash memory cell with high coupling rate using horned floating gate with fine HSG,” Symposium on VLSI Technology, p.104-105, 1998.
[6] A. Fazio, “0.13um logic + flash: technology and applications,” Non-Volatile Semiconductor Memory Workshop, 2000.
[7] D. L. Lee, The Improvement of Hot Carrier Reliability Issues on Embeddable Low Power Dinor Flash Cell With STI Structure, M.D., National Taipei University of Technology, Taipei, 1999.
[8] C. H. Huang, The Study of STI Corner Effect on Advanced Flash Memory, M.D., National Taipei University of Technology, Taipei, 2000.
[9] 徐清祥, 沈士傑,「快閃式記憶體結構及其操作模式」,電子月刊,第四卷,第七期,1998,第106-107頁。
[10] M. M. Ashot, Flash Memory Characterization, Ph.D., University of Yale, Connecticut, 2002.
[11] B. Rossler and R. Muller, ”Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell,” IEEE Transactions on Electron Device, vol.24, p.806, 1992.
[12] M. Lenzinger and E. H. Snow,“Fowler-Nordheim Tunneling into Thermally Grown SiO2,” Joumal of Applied Physics, p.278, 1969.
[13] Programmable Microelectronics Corp, Pm25LV/Pm25LV010, Data Sheet, 2004.

[14] Programmable Microelectronics Corp, Pm25LV010A/020A/040A, Data Sheet, 2004.
[15] SAMSUNG Electronics, K9F1208U0A, Data Sheet, 2004.
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