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研究生:曾仁溥
研究生(外文):Jen-Pu Tseng
論文名稱:應用多重演算法在FPGA系統設計之軟硬體分割
論文名稱(外文):Hardware-Software Partitioning Using Multiple Algorithms for FPGA Systems
指導教授:李宗演李宗演引用關係
指導教授(外文):Trong-Yen Lee
口試委員:熊博安蔡加春
口試委員(外文):Pao-Ann HsiungChia-Chun Tsai
口試日期:2005-06-23
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:76
中文關鍵詞:軟硬體共同設計軟硬體分割基因演算法模擬退火演算法全域計數搜尋演算法FPGA
外文關鍵詞:Hardware-Software CodesignHardware-Software (HW-SW) PartitioningGenetic AlgorithmSimulated Annealing AlgorithmGlobal Enumerated Search AlgorithmFPGA
相關次數:
  • 被引用被引用:1
  • 點閱點閱:244
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  • 下載下載:5
  • 收藏至我的研究室書目清單書目收藏:0
傳統上在設計一個系統時是軟體與硬體分開設計,而系統元件何者該為硬體或軟體則依賴設計者的經驗來決定;然而這種設計方式在整合與測試階段將花費更多的時間在系統之修正上。同時軟體與硬體分別各自實現出來再做整合,其效能的改進空間就變的相當有限。為了解決這些缺憾並提升系統效能,以軟硬體共同設計的方法將可改善以上的缺點。而軟硬體共同設計的重要步驟就是系統軟硬體的分割。在本論文中,我們應用基因演算法、模擬退火演算法以及全域計數搜尋演算法來發展一套軟硬體的分割工具,以代替傳統粗糙的手動分割,並依據使用者設定之系統規格的限制在系統執行時間、記憶體需求、所需的花費以及邏輯閘數等等,以做系統軟硬體分割之限制。同時本論文中也說明如何操作使用這一套工具介面以及詳述演算法的應用,本論文使用Xilinx XC2V1000 FPGA系統平台並以邊緣偵測與JPEG設計兩個例子來驗證我們所設計之軟硬體分割工具在FPGA系統設計的實用性與便利性。
Traditionally, the design of hardware and software parts in a system is processed independently, and the issues of hardware-software(HW-SW) partitioning almost decides by the experiences of designers. As the result, the design framework usually shows the errors and mismatch in the last stage after software and hardware had already been carried out. For this reason, it is difficult to turn the design to improve its performance and achievement. Due to those disadvantages of traditional design methodology, the HW-SW codesign is becoming a novel and practical solution to modern system design research area. The HW-SW partitioning is an important step in HW-SW codesign. Therefore, we propose a partitioning tool using genetic algorithm, simulated annealing algorithm and global enumerated search algorithm to implement in the system partitioning. We develop a friendly GUI (Graphic User Interface) for user in the partitioning tool. Finally, we use two design examples, Edge-Detection and JPEG design in digital image processing, to demonstrate the feasibility of our proposed hardware-software partitioning tool on the Xilinx FPGA system platform.
中文摘要…………………………………………………………………………………………i
英文摘要………………………………………………………………………………………..ii
致謝………………………………………………………………………………………….…iii
目錄……………………………………………………………………………………………..iv
表目錄………………………………………………………………………………………….vi
圖目錄…………………………………………………………………………………………vii第一章 導論…………………………………..……………………………………………….1
1.1簡介……………………………………………………………………………….1
1.2研究動機與目的……………………………………………………………….…4
1.3本論文之貢獻……………………………………………………………..……...5
1.4論文架構………………………………………………………………………….5第二章 相關文獻探討………………………..……………………………………….………7 2.1相關的分割演算法………………………………………………….……………8
2.2 FPGA系統的相關研究………………………………………………….……...10第三章 軟/硬體分割………………………….………………………………………..……12
3.1 CDFG (Control and Data Flow Graph)介紹……….…………………….....….13 3.2軟/硬體分割演算法………………….………………………………….………14第四章 使用者圖形介面設計與演算法之比較……..…………………………………..…32 4.1工具介面操作(GUI) ……………………………………………………………32 4.2演算法之時間與分割結果比較…………………………………………...……44第五章 實驗結果……………………………..…………………………………………...…47 5.1邊緣偵測…………………………………………………………….….……….47 5.2影像壓縮.………………………………………………………………………..51第六章 結論…………………………..……………………………………………………...58

參考文獻………………………………………………………………………………..……..59

附錄: 已刊登或接受之論文
1. Trong-Yen Lee, Jen-Pu Tseng, Yang-Hsin Fan, Chia-Chun Tsai, Wen-Ta Lee and Yuh-Shyan Hwang, “Hardware-Software Partitioning Tool Using Multiple Algorithms for FPGA Systems,” Proc. of the IEEE International Conference on Systems and Signals (IEEE ICSS 2005), Kaohsiung Taiwan, pp. 537-542, April
28-29, 2005………………………………..……………………………………………62
2. Trong-Yen Lee, Jen-Pu Tseng, Yang-Hsin Fan, Chia-Chun Tsai and Rong-Shue Hsiao, “Design of a Hardware-Software Partitioning Tool for FPGA Systems,” Proc. of the conference on VLSI/CAD , Paper No. 189, Hualien Taiwan, Aug. 9-12,
2005…………………………………………………...………………………...........…71
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