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研究生:廖敏雄
研究生(外文):Min-Hsiung Liao
論文名稱:前饋式雙取樣三位元四階帶通差和調變器設計
論文名稱(外文):THE DESIGN OF A DOUBLE-SAMPLED 3-BIT FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR BASED ON THE FEEDFORWARD TOPOLOGY
指導教授:黃淑絹黃淑絹引用關係
指導教授(外文):Shu-Chuan Huang
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:92
中文關鍵詞:四階帶通前饋式差和調變
外文關鍵詞:BANDPASSDELTA-SIGMA MODULATORFEEDFORWARDFOURTH-ORDER
相關次數:
  • 被引用被引用:0
  • 點閱點閱:155
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  • 下載下載:38
  • 收藏至我的研究室書目清單書目收藏:0
帶通差和調變器已經廣泛被運用在射頻通訊系統及測量儀器的製造,主要是因為帶通差和調變器比傳統的Nyquist-rate轉換器更能達到較高的解析能力。單位元量化的差和調變有著先天性的優勢,但可惜的是其產生的量化誤差相當大。因此可以使用多位元的量化方式來降低量化誤差,但前提是來自DAC元件不匹配所產生的誤差也就是非線性的缺陷能被解決。
前饋式帶通差和的架構比傳統的架構擁有幾項重要的優點。如前饋式架構較容易實現多位元量化的功能,不需要太複雜的電路並且實現之後的晶片面積較小。另外,利用雙取樣技術不僅能輕易地增加取樣頻率且還可舒緩對放大器的規格要求。
在本篇論文中,我們提出一前饋式架構為基礎之雙取樣三位元四階帶通差和調變器設計,其設計流程及相關設計軟體如下:先使用MATLAB模擬理想之系統層級電路,藉此得到最佳化的參數值。接下來用HSPICE模擬電晶體層級的電路,這樣可以加速整個設計的流程。此調變器的時脈頻率為50MHz(相當於100MHz的取樣頻率),輸入中心頻率為25MHz、頻寬1.25MHz的訊號,以HSPICE所做的模擬結果顯示,在最佳化架構下,其訊號雜訊比在輸入為 -9 dBFS是60.58dB、消耗功率為155.2mW。此電路是使用TSMC 0.35μm CMOS 2P4M製程參數進行模擬。
Bandpass ΔΣ converters have been used widely in RF communication systems and instrumentation filed due to the ability to obtain high resolution in the band of interest compared to the traditional Nyquist-rate converters. Delta Sigma modulation with a single-bit quantizer is inherently linear, but unfortunately also causes the quantization noise power to be quite large. It can be reduced by using a multi-bit quantizer if the nonlinearity error introducted by component mismatches of DAC can be solved.
Feedforward delta-sigma topologies have important system- and circuit- level advantages over traditional topologies. It is easy to implement multi-bits with less complexity and physical area for this topology. Additionally, double-sampled switched-capacitor (SC) technique provides a good method of increasing the sampling frequency without many efforts and relaxes the requirement of the Opamp.
In this thesis, a double-sampled 3-bit fourth-order bandpass delta-sigma modulator based on the feedforward topology is proposed. The design flow corresponding to the CAD tools is as followings. Using MATLAB, the optimal parameters are obtained by the system-level simulation. Then, the transistor level simulation with foundry device model is implemented by HSPICE. Finally, the layout of the whole circuit is accomplished with Virtuoso of CADENCE. The clock frequency is 50MHz (effective frequency would be 100MHz). The input signal bandwidth is 1.25MHz centered at 25MHz. The simulation results using HSPICE present a SNR of 60.58dB with -9dBFS input and power consumption of 155.2mW. The modulator is simulated by using the SPICE models of TSMC 0.35μm CMOS 2P4M process.
CONTENTS
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 The Three-bits Modultor 2
CHAPTER 2 DELTA-SIGMA CONVERTER 4
2.1 Basic Theory 4
2.1.1 Quantization 4
2.1.2 Nyquist Rate Conversion 5
2.1.3 Oversampling Conversion 7
2.2 Noise Shaping & LP to BP Transformation 10
2.3 Discrete-Time vs. Continuous-Time 14
2.4 Application of Bandpass Delta-Sigma Modulator 16
CHAPTER 3 BANDPASS DELTA-SIGMA MODULATORS 17
3.1 Design Structure 17
3.1.1 Resonator Types 17
3.1.2 Modulator Topologies 19
3.2 Resonator Design with Double-Sampled SC Circuit 22
3.2.1 Implementation of DD Resonator 22
3.2.2 Gain Mismatch in Double Sampling 26
3.2.3 Uneven Clock Phases 29
3.3 Multi-bits Quantization 29
3.3.1 Clocked Averaging 31
3.3.2 Random Averaging 32
3.3.3 Individual Level Averaging 32
3.3.4 Data Weighted Averaging 33
3.4 System Simulation with MATLAB 34
3.4.1 Non-ideal Factors of the System 35
3.4.2 Loop Gain Coefficient 36
3.4.3 Finite DC Gain and Unity-Gain Frequency 37
3.4.4 Capacitor Mismatch 38
3.4.5 Evaluation of Data Weighted Averaging 40
3.4.6 Simulation in Non-ideal Conditions 42
3.5 Circuit Level of the 3-bits BP ΔΣ Modulator 43
CHAPTER 4 CIRCUIT IMPLEMENTATION AND SIMULATION 49
4.1 Operational Amplifier 49
4.2 Comparator 54
4.3 Bias Circuit 57
4.4 Clock Generator 58
4.5 Switches 59
4.6 Simulation and Layout of Double-Sampled 3-bits 4th Order Bandpass Delta-Sigma Modulator Based on Feedforward Topology 62
CHAPTER 5 CONCLUSIONS 67
5.1 Conclusions 67
5.2 Future Work 67
5.2.1 Low Power Design 67
5.2.2 DWA implementation in FPGA 68
REFERENCES 69
APPENDICES 71
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[9] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., vol. 37, No. 12, pp. 737-738, June 2001.
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