臺灣博碩士論文加值系統

在本論文中，首先介紹射頻積體電路的設計概念與一些重要參數和低雜訊放大器的電路與雜訊分析。差動放大器的運用不僅能消除共模雜訊，還能降低偶次非線性效應，本文採用源極電感衰減方式及適當元件值的選取和電晶體源極低阻抗特性完成輸入及輸出阻抗匹配設計，來實現差動低雜訊放大器，亦使其所有結果有不錯特性表現。
使用台積電0.18μm CMOS製程參數來設計電路，且使用安捷倫Eesoft EDA-ADS模擬。於1.8V供應電壓下，差動放大器在5.2GHz模擬結果分別為: 輸入反射係數28.763dB，輸出反射係數14.999dB，雜訊指數為2.369dB，增益為12.884dB，P1dB為14.002dBm，OIP3為-3.56dBm
，功率損耗為15mW。

This thesis describes the RF IC design concept, several important parameters and circuit and noise analysis of low noise amplifier first. Differential LNA has not only the ability of rejecting the common-mode noise, but also the nature ability of canceling the even-order distortions. In this thesis, we design a differential LNA that has better result representations, through using of inductive source degeneration, choosing of suitable device parameter and low impedance characteristic of the transistor source side to achieve input and output impedance matching.
We employ TSMC CMOS 0.18μm process to design the LNA. With a supply voltage 1.8V, the simulation results for the differential LNA at 5.2GHz are as follows: input return loss is 28.763dB, output return loss is 14.999dB, gain is 12.884dB, noise figure is 2.369dB, P1dB is -14.002dBm, and the OIP3 is -3.56dBm. Power consumption is 15mW.

CONTENTS
PAGE
誌謝 I
ABSTRACT II
中文摘要 III
CONTENTS IV
LIST OF FIGURES VII
LIST OF TABLES X
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 3
CHAPTER 2 RF IC DESIGN CONCEPT 4
2.1 Introduction 4
2.2 S-Parameter 4
2.3 Stability and Gain 7
2.4 Linearity 9
2.4.1 Harmonics 10
2.4.2 Gain compression 11
2.4.3 Intermodulation 12
2.4.4 Third intercept point 14
2.5 Noise Figure 14
2.6 Dynamic Range 15
2.7 Sensitivity 16
CHAPTER 3 LOW NOISE AMPLIFIER DESIGN 18
3.1 Introduction 18
3.2 Noise analysis of a MOSFET Transistor 18
3.2.1 Drain current nosie 19
3.2.2 Induced gate noise 20
3.2.3 Distributed gate resistance noise 21
3.2.4 Shot Noise 22
3.2.5 Flicker Noise 23
3.2.6 Thermal Noise 24
3.3 LNA Topology 25
3.3.1 Single-ended Cascode LNA 25
3.3.2 Differential LNA 28
CHAPTER 4 DESIGN AND SIMULATION RESULTS 31
4.1 Single-ended Cascode LNA Design and simulation 31
4.1.1 Noise analysis of the LNA 31
4.1.2 Design and simulation results 34
4.2 Differential LNA design and simulation 39
4.3 Layout of Differential LNA 44
CHAPTER 5 CONCLUSION 45
REFERENCES 47

REFERENCES
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