臺灣博碩士論文加值系統

本論文中，我們使用FPGA(X2CV-1000, 0.18μm CMOS process, 3.3V power supply)設計AES-OCB模式運算，我們利用Verilog、Xilinx ISE 6.1、ModelSim 來設計、模擬與實現。其CLB slices為3552，最大的工作頻率為61.31Mhz，資料處理量為603Mbps。

In this thesis, we use FPGA(X2CV-1000, 0.18μm CMOS process, 3.3V power supply) to design AES_OCB mode operation. We use Verilog, Xilinx ISE 6.1 and ModelSim to design simulate and implement. The number of CLB slices is 3552.The operating clock rate is 61.31MHz. Data throughput is about 603Mbit/sec.

CONTENTS
Page
ABSTRACT (IN CHINESE) Ⅰ
ABSTRACT (IN ENGLISH) Ⅱ
ACKNOWLEDGMENTS Ⅲ
CONTENTS Ⅳ
LIST OF FIGURES Ⅵ
LIST OF TABLES Ⅷ
Chapter 1 Introduction
1.1 Overview 1
1.2 Design Approach 2
Chapter 2 The AES and OCB mode algorithm
2.1 Mathematical Preliminaries 3
2.1.1 The Finite field GF(28) 3
2.1.1.1 Addition 4
2.1.1.2 Multiplication 4
2.1.1.3 Multiplication by x 5
2.2 Specification 6
2.2.1 The State, the Cipher key and the number of rounds 7
2.2.2 The Round Transformation 7
2.2.2.1 The SubByte Transformation 8
2.2.2.2 The ShiftRow Transformation 10
2.2.2.3 The MixColumn Transformation 11
2.2.2.4 The AddRoundKey transformation 12
2.2.2.5 The Key Expansion 12
2.3 OCB mode of operation 15
Chapter 3 Architecture of the circuit
3.1 Design methodology 19
3.2 Architecture of the circuit 22
3.2.1 Round Component 23
3.2.2 Key Round Component 28
Chapter 4 Performance comparison and test setup
4.1 Performance comparison 29
4.2 The simulation 30
4.2.1 Pin description 30
4.3 Simulation result 32
Chapter 5 Conclusion 39
References 41

REFERENCE

[1] J. Daemen and V. Rijmen, AES submission document on Rijndael, Version 2, September 1999. (http://csrc.nist.gov/CryptoToolkit/aes/rijndael/Rijndael.pdf)
[2] P. Rogaway, M. Bellare, J. Black, T. Krovetz, “OCB A Block-Cipher Mode of Operation for Efficient Authenticated Encryption,” Eighth ACM Conference on Computer and Communications Security ACM CCS, ACM Press, 2001. pp. 196–205, http://www.cs.ucdavis.edu/rogaway.
[3] Chitu, Cristian and Manfred Glesner et al., “An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation,” Microelectronics Journal Volume: 36, February 2005, pp 139-146.
[4] F. X. Standaert et al., “A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES Rijndael,” The Field Programmable Logic Array Conference, Monterey, California , February 23-25, 2003, pp.216-224.
[5] C.C. Lu and S.Y. Tseng, “Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter Application-Specific Systems,” The IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2002, July 17-19, 2002, pp. 277 –285.
[6] X. Zhang, and K.K. Parhi, “Implementation Approaches for the Advanced Encryption Standard Algorithm,” IEEE Circuits and Systems Magazine 2 (4) (2002) pp. 25–46.
[7] P. Rogaway, Reference C Code, http://www.cs.ucdavis.edu/~rogaway.