在本論文裡，藉著考慮源-汲極寄生電阻分析的方法來研究MOSFET直流特性。我們以DRAM電路設計中所用的MOS元件實驗數據及TCAD模擬結果來驗証我們理論推導計算的準確性。研究上發現在線性區，源極及汲極電阻會同時導致汲極電流減少；但在飽和區，只有源極電阻會導致汲極電流減少。此外，由於通道長度和氧化層厚度的減少，會增加源-汲極電阻對汲極電流差額量的影響。
同時在本論文裡也提出一個演算法用來萃取MOSFET中的有效通道長度及源-汲極寄生電阻。研究上發現在LDD MOS元件中，有效通道長度及源-汲極寄生電阻和閘極電壓間有相互關係；隨著閘極電壓增加，有效通道長度會增加，源-汲極寄生電阻值會降低。除此之外，從實驗結果得知有效通道長度有溫度的的效應；當溫度降低時，有效通道長度會增加。

In this thesis, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source-drain parasitic resistance. Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the source and drain resistances can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the source-drain resistance increases with decreasing channel length and oxide thickness.
In addition, a measurement algorithm to extract the effective channel length and the drain-source parasitic resistance of MOSFET’s is presented in this thesis. It is shown that the effective channel length and the drain-source parasitic resistance of an LDD MOS device are gate-voltage dependent. The effective channel length increases and the source-drain parasitic resistance decreases with raising gate voltage. Besides, the effective channel length is temperature dependent from the experimental results. As the temperature lowers, the effective channel length increases.

Chinese Abstract…………………………………………… i
English Abstract…………………………………………… ii
Acknowledgement………………………………………… iii
Content…………………………………………………… iv
Table Caption……………………………………………… vi
Figure Caption…………………………………………… vii
List of Symbol…………………………………………… ix
Chapter1 Introduction…………………………………… 1
Chapter2 Physical Model for Drain Current………… 3
2-1 Threshold Voltage Model………………………… 3
2-2 Drain Current Model……………………………… 6
2-3 Result and Discussion……………………………… 12
Chapter3 Parameters Extraction………………………… 25
3-1 Extraction Algorithm……………………………… 26
3-2 Experimental Result and Discussion……………… 30
3-2-1 Gate Voltage Dependent……………………… 30
3-2-2 Temperature Effect of DL and Mobility……… 35
Chapter4 Conclusion……………………………………… 45
Reference………………………………………………… 46
Autobiography…………………………………………… 49

1.Y. El-Mansy, “MOS device and technology constraints in VLSI”, IEEE Trans. Electron Devices, vol. 29, p. 567, 1982.
2.M. C. Jeng, J. E. Chung, P. K. Ko, and C. Hu, “The effects of source/drain resistance on deep submicrometer device performance”, IEEE Trans. Electron Devices, vol. 37, p. 2408, 1990.
3.S. S. Chung, T. S. lin, and Y. G. Chen, “An efficient semi-empirical model of the I-V characteristics for LDD MOSFET’s”, IEEE Trans. Electron Devices, vol. 36, p. 1691, 1989.
4.Chen Kai, H. C. Wann, J. Duster, D. Pramanik, S. Nariani, P. K. Ko, and C. Hu, “An accurate semi-empirical saturation drain current model for LDD n-MOSFET”, IEEE Electron Device Letters, vol. 17, p.145, 1996.
5.V. Kasemsuwan, “An analytical transit time model for short channel MOSFET’s,” ICSE2000 proceedings, p. 72, 2000.
6.H. C. Chow and W. S. Feng, “An improved analytical model for short channel MOSFET’s”, IEEE Trans. Electron Devices, vol. 39, p. 2626, 1992.
7.A. Raychaudhuri, J. Kolk, M. J. Deen, and M. I. King, “A simple method to extract the asymmetry in parasitic source and drain resistance from measurement on a MOS transistor”, IEEE Trans. Electron Devices, vol. 42, p. 1388, 1995.
8.A. Ortiz-Conde, J. J. Liou, R. Narayanan, and F. J. Garcia Sanchez, ”On the physical mechanism contributing to the difference between drain and source resistances in short channel MOSFETs”, IEEE Hong Kong Electron Device Meeting proceedings, p.64, 1996.
9.Y. P. Tsvidis, Operation and Modeling of the Transistor, New York: McGraw-Hill, 1998.
10.H. J. Park, P. K. Ko, and C. Hu, “A charge sheet capacitance model of short channel MOSFET’s for SPICE”, IEEE Trans. Computer-Aided Design, vol. CAD-10, p. 376, 1992.
11.H. Brut, A. Juge, and G. Ghibaudo, “Physical model of threshold voltage in silicon MOS transistor including reverse short channel effect”, Electron. Lett., vol. 31, p. 411, 1995.
12.D. K. Schroeder, Semiconductor Material and Device Characterization, New York: Wiley, 1990.
13.J. A. Greenfield and R. W. Dutton, “Nonplannar VLSI device analysis using the solution of Poisson’s equation”, IEEE Trans. Electron Devices, vol. 27, p. 1520, 1980.
14.K. Y. Toh, P. K. Ko, and R. G. Meyer, ”An Engineering model for short channel MOS devices”, IEEE Journal of Solid-State Circuits, Vol. 23, p. 950, Aug. 1988.
15.H. C. Chow, W. –S. Feng, and J. B. Kuo, “Simple analytical model for short channel MOS devices”, IEEE Proceedings-G, Vol. 139, p. 405, June, 1992.
16.N. D. Arora, J. R. Hauser, and D. J. Roulston, “Electron and hole mobilities in silicon as a function of concentration and temperature”, IEEE Trans. Electron Devices, vol. 29, p. 292, 1982.
17.P. –K. Ko, “Approaches to scaling” in Advanced MOS Device Physics, N. G. Einsprunch and G. Gildenblat, Eds. (VLSI Electronics, vol. 18), New York: Academic, 1989.
18.Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, “ Threshold voltage model for deep-submicrometer MOSFET’s”, IEEE Trans. Electron Devices, vol. 40, p. 86, 1993.
19.“User Manual - Device Modeling Guide”, published by Celestry Design Technologies, 2001.
20.Suprem4 and Medici Manual, Avant! Corp., 2001
21.J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, “A new method to determine MOFET channel length”, IEEE Electron Devices Letters, vol. EDL-1, p. 170, 1980.
22.K. L. Peng and M. A. Afromowitz, “An improved method to determine MOSFET channel length”, IEEE Electron Devices Letters, vol. EDL-3, p. 360, 1982.
23.J. Whitfield, “A modification on an improved method to determine MOSFET channel length”, IEEE Electron Devices Letters, vol. EDL-6, p. 170, 1985.
24.P. I. Suciu and Palph L. Johnston, “Experimental derivation of the source and drain resistance of MOS transistors”, IEEE Trans. Electron Devices, vol. ED-27, p. 1846, 1980.
25.F. H. De La Moneda, H. N. Kotecha, and M. Shatzkes, “ Measurement of MOSFET constants”, IEEE Electron Devices Letters, vol. EDL-3, p. 10, 1982.
26.Genda J. Hu, Chi Chag and Yu-Tai Chia, “Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET’s”, IEEE Trans. Electron Devices, vol. ED-34, p.2469, 1987.
27.Steve Shao-Shiun Chung and Jenq-Sheng Lee, “A new approach to determine the drain-and-source series resistance of LDD MOSFET’s”, IEEE Trans. Electron Devices, vol. 40, p.1709, 1993.
28.M. H. Seavey, “Source and drain resistance determination for MOSFET’s”, IEEE Electron Devices Letters, vol. EDL-5, p. 479, 1984.
29.B. J. Sheu, C. Hu, P. K. KO, and F. C. Hsu, “ Source-and-Drain series resistance of LDD MOSFET’s”, IEEE Electron Devices Letters, vol. EDL-5, p. 365, 1984.
30.Avid Kamgar, “Miniaturization of Si MOSFET’s 77 K”, IEEE Trans. Electron Devices, vol. ED-29, p.1226, 1982.
31.Ch. Nguyen-Duc, S. Cristoloveanu, and G. Ghibaudo, “Low-temperature mobility behavior in submicron MOSFETs and related determination of channel length and series resistance”, Solid-State Electronics, vol. 29, p. 1271, 1986.
32.F. J. Garcia Sanchez, A. Ortiz-Conde, M. Garcia Nunez and R. L. Anderson, “Extracting the series resistance and effective channel length of short-channel MOSFETs at liquid nitrogen temperature”, Solid-State Electronics, vol. 37, p. 1943, 1994.
33.G. W. Taylor, “Subthreshold conduction in MOSFET’s”, IEEE Trans. Electron Devices, vol. ED-25, p.337, 1978.