臺灣博碩士論文加值系統

在本篇論文中，我們將討論低電壓低雜訊放大器的原理與設計。而裡面也包含時下熱門雙頻及超寬頻低雜訊放大器的原理與設計。我們採用了台積電0.18um CMOS的製程，且利用低電壓折疊式的技術去設計低雜訊放大器，最後將模擬結果與量測值來進行比較。
我們設計第一顆晶片為5.7 GHz 低雜訊放大器，應用於IEEE802.11a，它的量測值最大的增益為9.2 dB，輸出入的反射係數分別為-9.6 dB和-21.5 dB，而在5.7 GHz時，有著最小的雜訊值為3.1 dB，整體電路的消耗功率為7mW。第二顆晶片為2.4 /5.2 GHz同步雙頻低雜訊放大器，它的模擬結果為18.2 dB及14.2 dB的增益，在2.4及5.2 GHz的操作頻率下，雜訊值小於3 dB以下。
最後一顆晶片是應用於超寬頻系統的超寬頻低雜訊放大器，在3~10 GHz的整個操作頻段，最大及最小增益分別為13.16 dB及10.44 dB，因採用折疊式的技術，所以得到最小的雜訊值只有2.67 dB，而整個頻段的雜訊值都低於3.9 dB。
我們採用了安捷倫的電路設計軟體(ADS)來進行模擬，而這些電路的佈局及驗證採用了Cadance來進行。

In this dissertation, we discuss general low-voltage low noise amplifier principle and design. It includes nowadays dual band and ultra wideband low noise amplifier principle and design. Finally, we compare simulation results with measurement values. We adopt a low-voltage folded cascode topology to design the circuits of low noise amplifier for the receiver path of WLAN and WPAN. The circuits of low noise amplifier are based on 0.18um TSMC CMOS technology.
In WLAN application, measurement data shows that the amplifier achieves maximum power gain of 9.2 dB, input return loss of -9.6 dB, output return loss of -21.5 dB, and minimal noise figure of 3.1 dB on the 5.7 GHz while consuming 7 mW, For the dual-band LNA, simulation results get a power gain of 18.24 dB and 14.2 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure is less than 3 dB at both 2.4 GHz and 5.2 GHz bands. In WPAN application, the maximum and minimum power gain of ultra wideband LNA are 13.16 dB and 10.44 dB, respectively.
The -3dB bandwidth ranges between 3 GHz to 10 GHz in the circuit of the ultra wideband LNA. The minimum noise figure is also 2.67 dB owing to folded cascode technique. Hence, the noise figure is less than 3.9 dB within the range between 3 GHz to 10 GHz. In these circuits, the relatively high linearity was achieved without compromising power dissipation, gain and noise figure.
The simulation is performed by the Agilent Advance Design System (ADS) sofeware. The circuit layout and verification is fished by Cadance.

ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) ii
ACKNOWLEDGEMENT iv
CONTENTS v
TABLE CAPTIONS viii
FIGURE CAPTIONS ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Receiver Architectures Overview 2
1.2.1 Super-heterodyne Receivers 3
1.2.2 Double Down-Conversion Super-heterodyne Receivers 3
1.2.3 Direct-Conversion Receivers 7
1.2.4 Ultra-Wideband Radio Receivers 7
Chapter 2 Basic Concepts 11
2.1 Noise Analysis 11
2.1.1 Thermal Noise in MOSFETs 12
2.1.2 Flicker Noise 15
2.1.3 Noise Models of the CMOS Devices 16
2.2 Basic Topology of Low Noise Amplifier 19
2.2.1 Low Noise Amplifier Basic 19
2.2.2 Inductive Degeneration LNA 24
2.3 Optimizations of Low Noise Amplifiers 27
Chapter 3 Low Voltage LNA Design and Application 30
3.1 Introduction 30
3.2 Select Specifications 32
3.3 Narrow Band LNA Design 32
3.3.1 Select Devices of the LNA 35
3.3.2 Folded Cascode Circuit 35
3.3.3 Simulation and Measurement Results 38
3.4 Concurrent Dual-Band LNA Design 43
3.4.1 Dual-Band LNA Circuit 43
3.4.2 Image Rejection Filters and the Gain Tank 44
3.4.3 Simulation Results 47
3.5 Layout Consideration and Die Photograph 52
Chapter 4 Ultra wideband LNA Study and Realization 55
4.1 Introduction 55
4.2 Ultra Wideband LNA Design 59
4.2.1 Feedback Circuit and Input Matching 59
4.2.2 Shunt Peaking 60
4.3 Simulation Results 62
4.4 Layout Consideration and Die Photograph 63
Chapter 5 Conclusion 68
REFERENCE 70

TABLE CAPTIONS
Table 1 characteristic of WLNA standards…………………....33
Table 2 receiver performance requirements…………………..33
Table 3 Measured and simulated parameters of the LNA…….42
Table 4 concurrent dual-band LNA performance summary…..51
Table 5 a comparison between a typical narrowband and UWB system architecture……………………………………………57
Table 6 ultra-wideband LNA performance summary…………66


FIGURE CAPTIONS
Fig.1.1 bias components of receiver............................................4
Fig.1.2 the block diagram of super-heterodyne receiver…………………………………………………………4
Fig.1.3 image problem………………………………………………………....5
Fig.1.4 the choice of IF ( (a)high IF and (b)low IF)……………5
Fig.1.5 The block diagram of double down-conversion super-heterodyne receiver………………………………………9
Fig.1.6 The architecture of direct-conversion receiver………..10
Fig.1.7 The architecture of the ultra-wideband receiver………10
Fig.2.1 drain current noise model……………………………..13
Fig.2.2 gate noise model………………………………………13
Fig.2.3 flicker noise model……………………………………17
Fig.2.4 a standard MOS noise model………………………….18
Fig.2.5 equivalent input referred noise model………………...18
Fig.2.6 bias LNA architecture (a) resistive termination (b) 1/gm termination(c) shunt-series feedback (d) inductive degeneration…………………………………………………...22
Fig.2.7 Inductive degeneration small signal model…………...23
Fig.2.8 equivalent circuit of inductive degeneration LNA……23
Fig.3.1 design flow char………………………………………31
Fig.3.2 IEEE 802.11a specification…………………………...34
Fig.3.3 folded cascode circuit of the LNA……………………39
Fig.3.4 L-C tank………………………………………………39
Fig.3.5 simulation and measured results of input match……...40
Fig.3.6 simulation and measured results of output match…….40
Fig.3.7 simulation and measured results of power gain………41
Fig.3.8 simulation and measured results of noise figure……...41
Fig.3.9 measured result of one-tone test at 6.3 GHz………….42
Fig.3.10 concurrent dual-band receiver architecture………….45
Fig.3.11 circuit structure of concurrent dual band LNA……....45
Fig.3.12 series and shunt LC tank for image filter……………46
Fig.3.13 frequency planning of the dual-band image rejection.....................................................................................46
Fig.3.14 power gain of the dual-band LNA…………………...48
Fig.3.15 noise figure of the dual-band LNA…………………..48
Fig.3.16 input match of the dual-band LNA…………………..49
Fig.3.17 output match of the dual-band LNA…………………49
Fig.3.18 the IIP3 at the 2.4 GHz………………………………50
Fig.3.19 the IIP3 at the 5.7 GHz………………………………50
Fig.3.20 the layout of the folded cascode LNA……………….53
Fig.3.21 the layout of the dual-band LNA……………………53
Fig.3.22 die photographs of the cascode LNA chip…………..54
Fig.4.1 a typical narrowband and a UWB transceiver………...56
Fig.4.2 circuit structure of the ultra wideband LNA………….58
Fig.4.3 a doubly-terminated LC-ladder filter…………………58
Fig.4.4 shunt-peaked amplifier………………………………..61
Fig.4.5 power gain…………………………………………….64
Fig.4.6 noise figure……………………………………………64
Fig.4.7 input reflection coefficient and out reflection coefficient……………………………………………………..65
Fig.4.8 output power characteristics P1dB……………………..65
Fig.4.9 output power characteristics IIP3……………………..66
Fig.4.10 the layout of the ultra-wideband LNA…………

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