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研究生:謝明育
研究生(外文):Ming-yu Hsieh
論文名稱:寬頻低功率鎖相迴路設計與製作
論文名稱(外文):The Design and Implementation of a Wide-Range Power-Efficient CMOS Phase Locked Loop
指導教授:陳育鑚
指導教授(外文):Roger Yubtzuan Chen
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:73
中文關鍵詞:寬頻低功率鎖相迴路
外文關鍵詞:Wide-RangeCMOSVCOPLL
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本篇論文,提出一鎖相迴路,其中包含高靈敏度之相位/頻率檢測器(PFD )以及全差動可程式低雜訊的壓控震盪器。本文提出一種高速且低功率之相位/頻率檢測器,高頻操作下能提供較佳的線性度範圍以及頻率靈敏度。全差動可程式低雜訊的壓控震盪器,利用雙延遲路徑架構,能提供高頻且寬廣的頻率可調範圍,能藉由省電的多頻段控制達到操作頻率從85MHz到1.36GHz,依照我們針對壓控震盪器輸出抖動的模擬,證明全差動可程式低雜訊的壓控震盪器對於電源端擾動雜訊有較佳的性能。
A CMOS Phase-Locked Loop (PLL) equipped with a high-sensitivity Phase/Frequency Detector (PFD) and a differential range-programmable low-noise Voltage-Controlled Oscillator (VCO) is described. The PFD possesses a wide linear-range in its phase-detector characteristics and a high frequency-sensitivity. A full-switching low-noise differential delay cell is designed and employed to implement the differential range-programmable ring oscillator. Dual-delay path scheme is employed and leads to higher and wider output frequency range. A wide output-frequency range, from 85MHz to 1.36GHz, is achieved from the VCO in a power-efficient manner. The differential range-programmable ring oscillator shows substantial improvement in its output jitters, according to our jitter simulation in the presence of supply noise.
第一章 緒論
1-1 研究背景 1
1-2 研究動機 2
1-3 論文架構 3

第二章 鎖相迴路介紹
2-1 鎖相迴路簡介 4
2-2 鎖相迴路應用 6
2-3 相位頻率偵測器 9
2-3-1 相位頻率偵測器原理 9
2-3-2 相位頻率偵測器設計考量 12
2-4 充電幫浦 14
2-4-1 充電幫浦原理 14
2-4-2 充電幫浦性能指標 15
2-5 電壓控制震盪器
2-5-1 電壓控制震盪器原理 16
2-5-2 電壓控制震盪器設計考量 16
2-6 除頻器基本原理 22
2-7 迴路濾波器 23
2-8 鎖相迴路系統迴路數學模型 25

第三章 寬頻、省電鎖相迴路設計
3-1 簡介 27
3-2相位頻率偵測器 27
3-3寬頻低功率消耗之可調式多頻段壓控震盪器 37
3-4低死帶低諧波成份之充電幫浦 47
3-5可程式除頻器 51

第四章 鎖相迴路電路模擬與佈局
4-1 簡介 53
4-2 鎖相迴路系統參數設計 53
4-3 鎖相迴路之效能總覽 57
4-4 鎖相迴路之電路佈局 58
第五章 結論 61
參考文獻 62
參考文獻

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